1. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior

2. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Fabrication services n Educational services: – U.S.: MOSIS – EC: EuroPractice – Taiwan: CIC – Japan: VDEC n Foundry = fabrication line for hire.

3. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR -based design is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in  units  In our 0.5 micron process, = 0.25 microns.

4. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Fabrication processes n IC built on silicon substrate: – some structures diffused into substrate; – other structures built on top of substrate. n Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) n Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). n Silicon dioxide (SiO 2 ) is insulator.

5. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Photolithography Mask patterns are put on wafer using photo- sensitive material:

6. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub substrate

7. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont’d. Pattern polysilicon before diffusion regions: p-tub poly gate oxide

8. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont’d Add diffusions, performing self-masking: p-tub poly n+ p+

9. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont’d Start adding metal layers: p-tub poly n+ p+ metal 1 vias

10. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor structure n-type transistor:

11. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor layout n-type (tubs may vary): w L

12. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Drain current characteristics

13. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR 0.5  m transconductances From a 0.5 micron process: n n-type: – k n ’ = 73  A/V 2 – V tn = 0.7 V n p-type: – k p ’ = 21  A/V 2 – V tp = -0.8 V

14. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Current through a transistor Use 0.5  m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. n V gs = 2V: I d 0.5k’(W/L)(V gs -V t ) 2 = 93  A n V gs = 5V: I d = 1 mA

15. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Basic transistor parasitics n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance.

16. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Basic transistor parasitics, cont’d n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. – C gs = C ol W n Gate/bulk overlap capacitance.

17. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Latch-up n CMOS ICs have parastic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

18. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Parasitic SCR circuitI-V behavior

19. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Parasitic SCR structure

20. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

21. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Tub tie layout metal (V DD ) p-tub p+