1. Beam diagnostics developments at LAPP: Digital part CTF3 Collaboration Meeting 16-01-2007 Louis Bellier, Richard Hermel, Yannis Karyotakis, Jean Tassan, Sébastien Vilalte

2. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 2 Front-end Design divided in 3 parts: »Analog front-end board (4 inputs → 1 Σ and 2Δ) »Digital front-end board (sampling) »PCI acquisition board (far from radiation) 4 Δ1 Σ Δ2 ADC board Analog part Acquisition Near the beam <10m

3. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 3 Digital front-end Sampling Solution: Using the SAM analog memory. - Developed by the CEA for HESS2. - 2 memories (2x256 points) per channel ~ we need at least 300pts during 1,5 µs or 140 ns after CR (1 memory) - Sampling 200MSps or more. -Better delay line stability over 300MHz - Rad-Hard 200kRad → After the SAM: ADC rad-Hard, 14 bits, 800kSps. ↳ Synchronization with the SAM output → 35kRad technology due to FPGA CEA SAM Memory

4. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 4 Digital front-end principle FPGA 14 Σ ∆1 ∆2 SAM ADC SAM clk1 clk clk1 clk = 200MHzclk1 = 800kHz ADC SPECS Mezzanine board // Bus RJ 45 clk BlockingCTF3 clock

5. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 5 Digital front-end board

6. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 6 Acquisition 100m Master Board 100m Master board 4 channels Service box Specs slave Digital front-end board Digital front-end board Digital front-end board Specs slave Ethernet cable The chained specs mezzanines ( ~4 at least) Control room

7. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 7 Specs PCI Board

8. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 8 Sampling cycle 10 waiting for blocking signal 20 write in analog memory 40 sampling with ADC blocking pulse cell written 3x256 30 read analog memory data sampled data stored x3x256 41 write in FPGA ’s ram 50 send interruption to specs wait for read from specs 60 send the data data sent x3x256

9. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 9 Beam diagnostic Signals (Σ,Δ1,Δ2) Digital Front-end 13 Trigger SPECS Bus 1 1..4 SPECS Master 41 Gateway (Linux) 21

10. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 10 Disposition around the beam Digital Front-end boards in crate Ethernet cable to the acquisition ~5 meters Analog signals by RJ45 (SFTP cat.6) Analog front-end under the beam Power supply and control distribution board for analog part Blocking and CTF3 clock

11. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 11 Dosimeters BPI0608 8Gy BPI0622 7Gy BPI0645 45Gy 7Gy BPI0665 15Gy BPI0692 9Gy BPI0722 6Gy BPI0758 11Gy BPI0130 58Gy Integrated dose in Gray during the last run (3weeks) Girder

12. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 12 Evolution since the last meeting Tests and debug of the digital front-end prototype  Data transmission with the SPECS chain  Analog board configuration through SPECS and digital part Analog memory of 512 or 1024 disable =>2 memories of 256 points on next prototype Software development (link with FESA) Sum channel “positive and negative” Dosimeters around the TL1 during last commissioning 1 prototype still in production

13. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 13 Conclusion Testing one prototype during the next run. If digital part only after CR, just one analog memory necessary by channel. (pulse of 140ns) First Δ in front-end and final differences (ΔV and ΔH) in software after transmission. Software development with FESA. Possibility to install Lapp solution on CR after conclusive results on TL2. Installation on other part of the accelerator?

14. 16/01/2007CTF3 Collaboration Meeting Louis Bellier 14