1. 1 The University of Texas at Austin Ali Shafiee, A. Gundu, M. Shevgoor, R. Balasubramonian and M. Tiwari

2. Core1 $ $ MC Core0 $ $ 2 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

3. 3 Core 0 $ $ MC 3rd party software Core 1 $ $ Core 0: load changed Core 1: access latency changed Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

4. RD DM WR DM WR RD time Slot L Quantum Q= 4xL Goal: Minimize L Such that L is enough to transfer one read or one write While Satisfying cmd-to-cmd min time gaps Data Placement relaxes time gaps smart data placement  shorter L 4 0 0 1 1 2 2 3 3 CPU Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

5. Data Bus CA Bus Rank 0 Rank 1 Bank Memory Access = ACT+ CAS ACT CAS 5 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

6. 6 ACTCAS ACT00 CAS06 Rank(A)  Rank(B) ACTCAS ACT50 CAS04 Rank(0) Bank(A)  Bank(B) ACTCAS ACT511 CAS284 Rank(0) Bank(A)  Bank(A) 1 2 1 2 1 2 t BURST t RTRS t BURST t RRD t FAW t CCD t RCD t RAS t RC t RP t RTP Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

7. Rank-Part: Rank Partitioning Bank-Part: Bank Partitioning No-Part: No Partitioning Core 0 Core 1 Core 2 Core 0 Core 1 Core 2 Core 3 7 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

8. RD WR RD WR time Data Bus 0L 1L 2L 3L 4L 5L time CA Bus ACT CAS T RCD T CAS CAS ACT T RCD T CWD KL-T CAS KL-(T CAS +T RCD ) KL-T CWD KL-(T CWD +T RCD ) Fixed Periodic Transfer 8 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

9. Enough Time to Transfer No Collision on CA Bus L ≥T BURST +T RTRS  L ≥ 6 CAS(RD) ≠ CAS (WR) KL-11 ≠ K’L-5 Rank-Part  L=7 Bank-Part  L=15 No-Part  L=43 9 (K-K’)L ≠6  L≠6 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

10. R R W W R R R R W W R R W W W W L=15 R R W W R R R R W W R R W W W W L=6 L=15 Return to CPU en masse Q=120 Q=63 10 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

11. 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 L=43 Q=344 0 0 1 1 2 2 3 3 4 4 6 6 6 6 7 7 L=15 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Q=120 0 0 Memory Bank = + + 3x15=45>43 11 CPU 0 0 3 3 6 6 1 1 4 4 7 7 2 2 5 5 = Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

12. Simics Simics – 8 4-way superscalar cores – L1I (32K)/L1D (32KB)/L2 (1MB)  per core USIMM USIMM – 1channel, 8 ranks, 8 banks Benchmark Benchmark – SPEC 2006 – NPB Temporal Partitioning Compared with Temporal Partitioning (HPCA’14) 12 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

13. Increase OS complexity RANK PARTITIONINGNO PARTITIONINGBANK PARTITIONING PERFORMANCE NON-SECURE BASELINE 1.0 0.74 0.48 0.43 0.20 0.40 FS FS: RD/WR-REORDER FS: TRIPLE ALTERNATION TP 13 100% 12% 72% Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

14. 14 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies

15. Thank You 15 Avoiding Information Leakage in the Memory Controller with Fixed Service Policies