1. S4525A Peripherals & Enhanced FLASH 1 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 1 Peripherals & Enhanced FLASH New Peripherals Enhanced FLASH PIC16F87X and PIC16F62X Enhanced FLASH PIC16F87X and PIC16F62X

2. S4525A Peripherals & Enhanced FLASH 2 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 2 Peripherals & Enhanced FLASH PIC16F87X Features at a Glance l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l Two Capture/Compare/PWMs l USART l 9-bit addressable l High Speed Enhanced SPI  l All 4 SPI modes supported l Microwire  Support Master I 2 C  l Hardware Write to I 2 C devices In-Circuit-Serial Programming  l In-Circuit-Debugger l Parallel Slave Port

3. S4525A Peripherals & Enhanced FLASH 3 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 3 Peripherals & Enhanced FLASH PIC16F62X Features at a Glance l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l Capture/Compare/PWM l USART l 9-bit addressable l High Speed l 2 Comparators In-Circuit-Serial Programming  l Internal RC Oscillator

4. S4525A Peripherals & Enhanced FLASH 4 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 4 Peripherals & Enhanced FLASH Master SSP Module: I 2 C  Mode l PIC16F87X devices have the Master SSP. l SSPCON2 register is added. l SSPSTAT are new. l Code from PIC16C7X devices is 100% compatible.

5. S4525A Peripherals & Enhanced FLASH 5 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 5 Peripherals & Enhanced FLASH I 2 C Master Operation l There is a sequence of events during a transfer from Start bit to Stop bit: Start Bit Byte Writes Byte Reads Acknowledges Restart Conditions Stop Bit l The I 2 C Master is like a state machine. Cannot spool or queue events l The I 2 C module must be idle before starting a new event.

6. S4525A Peripherals & Enhanced FLASH 6 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 6 Peripherals & Enhanced FLASH I 2 C Master Mode

7. S4525A Peripherals & Enhanced FLASH 7 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 7 Peripherals & Enhanced FLASH SSP Mode Select Bits SSPM 0000SPI Master Mode, clock = Fosc/4 0001SPI Master Mode, clock = Fosc/16 0010SPI Master Mode, clock = Fosc/64 0011SPI Master Mode, clock = TMR2 output/2 0100SPI Slave Mode, clock = SCK pin, SS enabled 0101SPI Slave Mode, clock = SCK pin, SS disabled 0110I 2 C Slave Mode, 7-bit address 0111I 2 C Slave Mode, 10-bit address 1000I 2 C Master Mode, clock =Fosc/(4*(SSPADD+1)) 1011IC Firmware controlled Master Mode (slave idle) 1110I 2 C Firmware controlled Master Mode, 7-bit address 1111I 2 C Firmware controlled Master Mode, 10-bit address 2

8. S4525A Peripherals & Enhanced FLASH 8 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 8 Peripherals & Enhanced FLASH Bus Collision l The BCLIF flag bit (PIR2 ) indicates a bus collision. l Always check for bus collision, even if one master and one slave are the only devices on the bus. l Check for bus collision after every idle check. l Make sure that the event has completed and that any possible bus collisions were detected.

9. S4525A Peripherals & Enhanced FLASH 9 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 9 Peripherals & Enhanced FLASH Write Sequence l Any byte that is written out will generate 9 clocks l 8 clocks for data (SDA is an output). l 1 clock for acknowledge bit (SDA is an input). l State of acknowledge bit is in the ACKSTAT bit (SSPCON2 ). l The state of the acknowledge bit should be checked after idle and bus collision checks. l Write sequence: l Start bit l Control/Address with R/W = 0 l Address byte l Data byte l Stop bit

10. S4525A Peripherals & Enhanced FLASH 10 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 10 Peripherals & Enhanced FLASH Read Sequence l A read sequence will only generate 8 clocks. l The master must acknowledge the slave. l Write ACK state to ACKDT bit (SSPCON2 ),value used on SDA. l Set the ACKEN bit (SSPCON2 ), starts one clock cycle on SCL. l Read Sequence: l Start bit l Control/Address with R/W = 0 l Address l Restart l Control/Address with R/W = 1 l Read Byte l Stop bit l Last byte read from slave should be NACKed by the master.

11. S4525A Peripherals & Enhanced FLASH 11 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 11 Peripherals & Enhanced FLASH ACK Polling l Determines if the serial EEPROM can accept more data. l ACK Polling sequence: l Start bit l Control/Address with R/W = 0 l Check to see if the serial EEPROM acknowledged (ACKSTAT = 0) l If serial EEPROM acknowledged then continue l Otherwise, wait for serial EEPROM to acknowledge by: l Restart l Control/Address with R/W = 0 l Check ACKSTAT

12. S4525A Peripherals & Enhanced FLASH 12 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 12 Peripherals & Enhanced FLASH SPI Mode Block Diagram SPI  Mode Block Diagram

13. S4525A Peripherals & Enhanced FLASH 13 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 13 Peripherals & Enhanced FLASH SPI Module SCK (CKP = 0,CKE =0) SCK (CKP = 1,CKE =0) SCK (CKP = 0,CKE =1) SCK (CKP = 1,CKE =1) SDO (CKE=0) SDO (CKE=1) SDI (SMP=0) SDI (SMP=1) (Microwire ® ) b7 b6 b5 b4 b3 b2 b1 b0

14. S4525A Peripherals & Enhanced FLASH 14 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 14 Peripherals & Enhanced FLASH I 2 C Master Mode Exercise 2 l Configure I 2 C module for 100KHz clock. l Read the temperature of the I 2 C sensor DS1721. l Read the temperature 128 times to get an average.

15. S4525A Peripherals & Enhanced FLASH 15 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 15 Peripherals & Enhanced FLASH Bank0 Bank1 Bank2 Bank3 Special Function Registers PIC16C77 PIC16F877 00h 180h 1Fh 19Fh 00h 1Fh 180h 19Fh