1. Lecture 1: Review of Computer Organization
Operating System
Fall 2014

2. What is Operating System?
Operating system is a program that acts as an intermediary between a user of a computer and the computer hardware.
Main GOALS of an OS:
To make the computer system convenient to use
To use the computer hardware in an efficient manner

3. Four Elements of a Computer System
Processor (CPU)
Control the operation of the computer and its data processing functions.
Main Memory
Stores data and programs
RAM - random access memory
I/O Modules
Auxiliary storage like disk drives, tape drives
Printers, terminals, monitors
System Bus
Provides for transfer of data among processors, main memory, and I/O modules

4. Computer Organization
CPU PC IR
Execution
Unit
MAR
MBR
I/O AR
I/O BR
I/O module …
DATA
Instruction
buffer
MAIN MEMORY
System
Bus 1
n-1
n-2

5. CPU (Processors) Registers
A processor includes a set of registers that provide a level of memory faster than main memory.
User-visible Registers
Control and Status Registers

6. User-visible Registers
Many instructions operate on data sitting on working registers.
Since registers are faster than main memory, it is better that data be moved to registers before operating on them.
May be referenced by the machine language that the processor executes
available to all programs - application programs and system programs.
Types of registers:
Data registers
Address registers
For indirect addressing
For index register
For segment pointer
For stack pointer

7. Control and Status Registers
Program Controller (PC) – contains the address of an instruction to be fetched
Instruction Register (IR) – contains the instruction most recently fetched
Memory Address Register (MAR)
Memory Buffer Register (MBR)
I/O Address Register (I/O AR)
I/O Buffer Register (I/O BR)
Processor Status Word (PSW)
condition codes or flags
interrupt enable/disable
user/supervisor mode

8. Instruction Cycle Start Fetch next instruction Execute Halt
Fetch Cycle
Execute Cycle
Opcode
Address of Operand
Instruction Format
Sign
magnitude
Integer Format
exponent
magnitude
Floating point Format
Sign

9. Actions of CPU (Types of Instructions)
Processor-Memory Data Transfer
Processor-I/O Data Transfer
Data Processing
Arithmetic or logic operation on data
Control
Alter sequence of execution

10. Interrupts An interruption of the normal sequence of execution
Improve processing efficiency
Allows the processor to execute other instructions while an I/O operation is in progress

11. Interrupts - Classes of Interrupts
Program
arithmetic overflow or underflow
division by zero
attempt to execute an illegal machine instruction
reference outside user’s memory space
Timer
I/O
Hardware Failure

12. Interrupts –Interrupt Handler
A program that determines nature of the interrupt and performs whatever actions are needed
Control is transferred to this program
Generally part of the operating system

13. Interrupts and the Instruction Cycle
Start
Fetch next
instruction
Execute
Fetch Cycle
Execute Cycle
Interrupts
Disabled
Check for interrupt
and process interrupt
Enabled
OS Fall 2005

14. Interrupt Cycle Processor checks for interrupts
If no interrupts, fetch the next instruction for the current program
If an interrupt is pending, suspend execution of the current program, and execute the interrupt handler

15. Program Flow of Control without and with Interrupts
User Program
WRITE
(1)
(2)
(3)
I/O Program
I/O Command
END
(4)
(5)
Interrupt Handler
Interrupts
User Program
WRITE
(1)
(2)
(3)
I/O Program
I/O Command
END
(4)
(5)
No interrupts

16. Simple Interrupt Processing
Device controller or other
Hardware generates an interrupt
Processor finished
execution of current instruction
Processor signals
acknowledgement of interrupt
Processor pushes PSW
and PC onto control stack
Processor loads new
PC value based on interrupt
Hardware
Save remainder of
process state information
Process interrupt
Restore process
state information
Restore old
PSW and PC
Software

17. Multiple Interrupts Two methods:
Disable other interrupts while processing one interrupt
Assign priorities to different interrupts. Interrupts at higher priority can interrupt lower ones

18. Memory Registers Cache Main memory Electronic disk Magnetic disk
Optical disk
Magnetic tapes
Decreasing cost per bit
volatile
Increasing capacity
Increasing access time
Decreasing frequency of access
of the memory by the processor
nonvolatile

19. Caching
Important principle, performed at many levels in a computer (in hardware, operating system, software)
Information in use copied from slower to faster storage temporarily
Faster storage (cache) checked first to determine if information is there
If it is, information used directly from the cache (fast)
If not, data copied to cache and used there

20. Cache Invisible to operating system Increase the speed of memory
Processor speed is faster than memory speed
Contain a portion of main memory
CPU
Cache
Main
memory
Word
Transfer
Block

21. Cache Design Cache size Block size Mapping function
Determine which cache location the block will occupy
Replacement algorithm
Determines which block to replace
Least-Recently-Used(LRU) algorithm
Write policy
When the memory write operation takes place
Can occur every time block is updated
Can occur only when block is replaced

22. I/O Communication Techniques
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)

23. Programmed I/O I/O module performs the action, not the processor
Issue Read
command
to I/O module
Read status of
I/O module
Check status
Read word from
Write word into
Main memory
Done?
Not
ready
yes
Next instruction no
CPU->I/O
I/O -> CPU
Error
condition
CPU->memory
I/O module performs the action, not the processor
Sets appropriate bits in the I/O status register
No interrupts occur
Processor checks status until operation is complete

24. Interrupt-Driven I/O
Issue Read
command
to I/O module
Read status of
I/O module
Check status
Read word from
Write word into
Main memory
Done?
ready
yes
Next instruction no
CPU->I/O
I/O -> CPU
Error
condition
CPU->memory
Do something
else
Interrupt
Processor is interrupt when I/O module ready to exchange data
Processor is free to do other work
No needless waiting
Consumes a lot of processor time because every word read or written passes through the processor

25. Direct Memory Access
Transfer a block of data directly to or from memory
An interrupt is sent when the task is complete
The processor is only involved at the beginning and end of the transfer
Issue Read
command
to I/O module
Read status of
DMA module
Next instruction
CPU->DMA
DMA -> CPU
Do something
else
Interrupt

26. End of lecture 1
Thank you!