1. Global Muon Trigger / RPC Interface Warsaw and Vienna Groups RPC Electronics System Review Warsaw, 8 July 2003 presented by Claudia-Elisabeth Wulz

2. RPC ESR, Warsaw, July 2003 C. - E. Wulz2 Global Muon Trigger Overview Output: 8 bit , 6 bit , 5 bit p T, 2 bits charge/synch, 3 bit quality, 1 bit MIP, 1 bit Isolation Inputs: 8 bit , 6 bit , 5 bit p T, 2 bits charge, 3 bit quality, 1 bit halo/eta fine-coarse Best 4  4  RPC brl 4  DT 4  CSC 4  RPC fwd 252 MIP bits 252 Quiet bits

3. RPC ESR, Warsaw, July 2003 C. - E. Wulz3 Input from RPC to GMT 8 bit  :2.5 0 steps, bin 0 at interval 0 0 - 2.5 0 OK 5 bit p T :Non-linear scale, must be indentical for RPC and GMT. p T =0 means no muon.OK 3 bit quality:New definition since 6-plane algorithm.OK ORCA to be updated. 6 bit  :Tower number for positive side. For negative side to be decided.? Halo bit / fine eta bit: Not relevant for RPC‘s. 1 bit charge: 1 - negative, 0 - positiveOK 1 bit charge validation: now computed by RPCOK 3 bits bunch counter:B2 B1 B0OK 1 bit bunch crossing zero: BC0OK 1 bit synchronization error: SEOK 1 bit clock:CLKOK

4. RPC ESR, Warsaw, July 2003 C. - E. Wulz4 Bit Assignment and Hardware Assignment of input bits LVDS drivers and receivers Suggested: SN75LVDS387 16 bit LVDS driver SN75LVDT386 16 bit LVDS receiver Cables for parallel transfer Suggested: Madison cable: 34 pairs, 28 AWG, halogen free (order together with Wisconsin group)

5. RPC ESR, Warsaw, July 2003 C. - E. Wulz5 Assignment of LVDS Signals

6. RPC ESR, Warsaw, July 2003 C. - E. Wulz6 Connectors SCSI-3 type connector Wire pairs: w1-w2 = pin 35-1, w3-w4 = pin 36-2etc.

7. RPC ESR, Warsaw, July 2003 C. - E. Wulz7 GMT in Underground Counting Room

8. RPC ESR, Warsaw, July 2003 C. - E. Wulz8 Global Trigger / Global Muon Trigger Crate

9. RPC ESR, Warsaw, July 2003 C. - E. Wulz9 Layout of USC55 Counting Room Racks Lower Floor Links ( ~5ns/m) + LVDS driver/receiver stages should not contribute more than 2-3 bx to latency. Need estimate of cable length.

10. RPC ESR, Warsaw, July 2003 C. - E. Wulz10 GMT Hardware Status  GMT consists of  3 pipeline synchronizing boards (PSBs)… prototype available  1 GMT logic board… logic design completed  FPGA design for GMT logic board in progress  Milestones  Dec 2002: logic design completed… completed  Dec 2003: FPGA design done… progress as planned  Jun 2004: GMT available  Oct 2004: GMT tested

11. RPC ESR, Warsaw, July 2003 C. - E. Wulz11 URL’s and Documentation This talk can be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/ GMT_RPC_warsaw.ppt Detailed information about the Global Muon Trigger and the Global Trigger is available on the HEPHY Vienna web sites: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger Draft interface document Regional Muon Trigger / GMT to be finalized: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/notes/ Reg_to_GMT_Note_0.91.pdf

12. RPC ESR, Warsaw, July 2003 C. - E. Wulz12 Conclusions and Acknowledgements Most of the issues of the RPC/GMT interface are settled. To be done: - Choice of cables and connectors - Coding of  - Update RPC and GMT codes in ORCA - Update documentation Special thanks to M. Kudla, H. Sakulin and A. Taurok.