1. Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal

2. This schematic, which has already been considered in previous tutorials, will be used to illustrate various simulation modes Hex outputs 3A 1 0 S 0...S 7 Data can be entered from DIP switchers and the result can be displayed on LCD. RFSM

3. Rg STM T1T1 TRTR p D1D1 DRDR y1y1 yNyN PM x1x1 xLxL LM external inputs external outputs current state (CS) next state (NS) programmable multiplexer (PM) state transition memory (STM) state transition RAM (STRAM) state transition ROM (STROM) See details in: V. Sklyarov, Reconfigurable models of finite state machines and their implementation in FPGAs. Journal of Systems Architecture, 47, 2002, pp. 1043-1064. Available on webct.ua.pt level memory (LM) LRAM LROM

4. Begin y1y1 y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a0a0 a1a1 a2a2 a3a3 a4a4 extra state a0a0 See details in S. Baranov, ”Logic Synthesis for Control Automata”. Kluwer Academic Publishers, 1994. RAM M x1x1 0 R-1 fdc 0 fdc 2 y1y1 Output RAM y4y4 x2x2 a0a0 a1a1 a2a2 a3a3 y2y2 y3y3 y 3,y 4 1 x1x1 x1x1 x1x1 x2x2 a4a4 x1x1 x1x1 x1x1 x2x2 y1y1 The same RAM block

5. Begin y1y1 y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a0a0 a1a1 a2a2 a3a3 a4a4 extra state a0a0 RAM M x1x1 0 R-1 fdc 0 fdc 2 y1y1 Output RAM y4y4 x2x2 K(a 0 )=000; K(a 1 )=001; K(a 2 )=010; K(a 3 )=011; K(a 4 )=100; 000 001 010 001 011 001 100 010 address data 0000 001 0001 001 0010 100 0011 000 0100 100 0101 000 0110 100 0111 000 1000 010 1001 011 1010 - - - 1011 - - - 1100 - - - 1101 - - - 1110 - - - 1111 - - - address data 000 0001 001 0010 010 0100 011 1100 100 0000 address data y1y1 y2y2 y3y3 y4y4 a3a3 a4a4 a3a3 a4a4 y4y4 In the general case this changes the behavior of the FSM, increases the number M of states, and reduces the speed of state transitions

6. Dummy states are used just for providing reconfigurability and they should not be stored in the FSM register. Thus the outputs of reprogrammable block of the first level have to be linked with inputs of similar block for the next level. The outputs of such block of the last level will change the state of the FSM register. So any multidirectional state transition can be realized without any specific constraint. Dummy states might appear only in between levels during propagation of the respective signals in the combinational circuit. Thus they practically do not reduce the speed of state transitions.

7. y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a1a1 a2a2 a3a3 a4a4 dummy state a0a0 001001 100100 clock rising edge a1a1 a3a3 0 0 1 1 011011 011011

8. process(clk,rst) variable tmp,count_ones : integer range 8 downto 0; begin if rst = '1' then count_ones := 0; tmp := 0; elsif falling_edge(clk) then if y1 = '1' then result <= conv_std_logic_vector(count_ones,4); end if; if y2 = '1' then count_ones := 0; tmp := 0; end if; if y3 = '1' then tmp := tmp+1; end if; if y4 = '1' then count_ones := count_ones+1; end if; if tmp > 7 then x1 <= '1'; else x1 <= '0'; x2 <= in_vector(tmp); end if; end process; a0a0 a1a1 a2a2 a3a3 y1y1 y2y2 y3y3 y 3,y 4 1 x1x1 x1x1 x1x1 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 Begin y1y1 y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a0a0 a1a1 a2a2 a3a3 a4a4 dummy state a0a0 a) b) c) WE Output RAM WE MRAM2 WE MRAM1 WE LRAM2 WE LRAM1 4 bits DATA Y X { y 1,y 2, y 3,y 4 } { x 1,x 2 } RFSM datapath d)

9. RAM M x0x0 x L-1 0 R-1 G blocks fdc 0 fdc R-1 y0y0 Output RAM y N-1 Y X RAM M x0x0 x L-1 0 R-1 X XY FSM_CC: for i in 1 to G generate level_PM: level generic map(L=>8,R=>3,N=>3) port map(clk,we_a(i-1),wem_a(i-1),di,ar,X,dummy_state(i-1),dummy_state(i)); end generate FSM_CC; FSM_reg: for i in 0 to R-1 generate REG:FDC port map (dummy_state(0)(i),not clk,rst,dummy_state(G)(i)); end generate FSM_reg; level 1level G dummy_state(1) dummy_state(G-1) level dummy state input level dummy state output SEL MUX_OUT external inputs for reloading RAM blocks reset clock

10. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Gen_Mux is generic (L : integer := 8; R : integer := 3); Port ( SEL : in std_logic_vector(R-1 downto 0); X : in std_logic_vector(L-1 downto 0); MUX_OUT : out std_logic); end Gen_Mux; architecture Behavioral of Gen_Mux is begin MUX_OUT <= X(conv_integer(SEL)); end Behavioral; fdc 0 fdc 2 y1y1 Output RAM y4y4 M x1x1 0 R-1 x2x2

12. clock generator is not shown user constraint file

13. RAM M x1x1 0 R-1 x2x2 entity RAM is generic (N : integer := 3; -- number of outputs deep : integer := 8; -- number of words R : integer := 3); -- number of inputs port ( clk : in std_logic; we : in std_logic; -- write enable di : in std_logic_vector(N-1 downto 0); -- data to write a : in std_logic_vector(R-1 downto 0); -- address to read ar : in std_logic_vector(R-1 downto 0); -- address to write spo : out std_logic_vector(N-1 downto 0)); -- RAM output end RAM; architecture Behavioral of RAM is type ram_type is array (deep-1 downto 0) of std_logic_vector (N-1 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(ar)) <= di; end if; end process; spo <= RAM(conv_integer(a)); end Behavioral; y1y1 Output RAM y4y4

14. entity Prog_Mux is generic (L : integer := 8; R : integer := 3); Port ( clk : in std_logic; we : in std_logic; di : in std_logic_vector(R-1 downto 0); ar : in std_logic_vector(R-1 downto 0); state : in std_logic_vector(R-1 downto 0); X : in std_logic_vector(L-1 downto 0); MUX_OUT : out std_logic); end Prog_Mux; architecture Behavioral of Prog_Mux is component Gen_Mux is generic (L : integer; R : integer); Port ( SEL: in std_logic_vector(R-1 downto 0); X: in std_logic_vector(L-1 downto 0); MUX_OUT: out std_logic); end component; component RAM is generic (N : integer := 3; deep : integer := 8; R : integer := 3); port ( clk : in std_logic; we : in std_logic; di : in std_logic_vector(N-1 downto 0); a : in std_logic_vector(R-1 downto 0); ar : in std_logic_vector(R-1 downto 0); spo : out std_logic_vector(N-1 downto 0)); end component; signal link : std_logic_vector(R-1 downto 0); begin MUX : Gen_Mux generic map(L=>8,R=>3) port map(link,X,MUX_OUT); MUX_RAM : RAM generic map(N=>3,deep=>8,R=>3) port map(clk,we,di,state,ar,link); end Behavioral; M RAM link

15. RAM M x1x1 0 R-1 x2x2 entity level is generic (L : integer := 8; R : integer := 3; N : integer := 3); Port ( clk : in std_logic; we : in std_logic; wem : in std_logic; di : in std_logic_vector(N-1 downto 0); ar: in std_logic_vector(R downto 0); X: in std_logic_vector(L-1 downto 0); ds: in std_logic_vector(R-1 downto 0); T: out std_logic_vector(N-1 downto 0)); end level; architecture Behavioral of level is component Prog_Mux is -- see the previous slide end component; component RAM is -- see the previous slide end component; signal m_out : std_logic; signal composed : std_logic_vector(R downto 0); begin composed <= ds & m_out; level_CC: Prog_Mux generic map(L=>8,R=>3) port map(clk,wem,di,ar,ds,X,m_out); level_RAM: RAM generic map(N=>3,deep=>16,R=>4) port map (clk,we,di,composed,ar,T); end Behavioral; component Prog_Mux is generic (L : integer := 8; R : integer := 3); Port ( clk : in std_logic; we : in std_logic; di : in std_logic_vector(R-1 downto 0); ar : in std_logic_vector(R-1 downto 0); state : in std_logic_vector(R-1 downto 0); X : in std_logic_vector(L-1 downto 0); MUX_OUT: out std_logic); end component; ds – dummy state

16. entity RAM_FSM is generic (L : integer := 8; R : integer := 3; N : integer := 4; G : integer := 2); Port ( clk: in std_logic; we_a: std_logic_vector(G-1 downto 0); wem_a: std_logic_vector(G-1 downto 0); weo: std_logic; di : in std_logic_vector(N-1 downto 0); ar: in std_logic_vector(R downto 0); rst: in std_logic; X: in std_logic_vector(L-1 downto 0); Y: out std_logic_vector(N-1 downto 0)); end RAM_FSM; architecture Behavioral of RAM_FSM is component FDC generic (INIT : bit := '1'); port ( Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; component level is -- see the previous slide end component; component RAM is -- has been already considered end component; component level is generic (L : integer := 8; R : integer := 3; N : integer := 3); Port ( clk : in std_logic; we : in std_logic; wem : in std_logic; di : in std_logic_vector(N-1 downto 0); ar : in std_logic_vector(R downto 0); X : in std_logic_vector(L-1 downto 0); ds : in std_logic_vector(R-1 downto 0); T : out std_logic_vector(N-1 downto 0)); end component;

17. type between_levels is array (G downto 0) of std_logic_vector (R-1 downto 0); signal dummy_state : between_levels; begin FSM_reg: for i in 0 to R-1 generate REG : FDC port map (dummy_state(0)(i),clk,rst,dummy_state(G)(i)); end generate FSM_reg; FSM_CC: for i in 1 to G generate level_PM: level generic map(L=>8,R=>3,N=>3) port map(clk,we_a(i-1),wem_a(i-1),di,ar,X,dummy_state(i-1),dummy_state(i)); end generate FSM_CC; output_RAM:RAMgeneric map(N=>4,deep=>8,R=>3) port map (clk,weo,di,dummy_state(0),ar,Y); end Behavioral; R is the size of FSM register G is the number of levels The number of levels G defines maximum number of FSM inputs, which can be tested during one clock cycle

18. entity controller is port ( clk : in std_logic; rst : in std_logic; reset : out std_logic; prog : out std_logic_vector(5 downto 0)); end controller; architecture Behavioral of controller is signal count : std_logic_vector(5 downto 0); begin process(clk,rst) variable tmp : integer; begin if rst = '1' then count '1'); tmp := 0; reset <= '1'; elsif rising_edge(clk) then if tmp < 56 then count <= count + 1; tmp := tmp+1; else reset <= '0'; end if; prog <= count; end process; end Behavioral; This block reads 56 words of ROM and writes these words to RFSM RAM blocks After programming the controller resets RFSM

19. Begin y1y1 y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a0a0 a1a1 a2a2 a3a3 a4a4 dummy state a0a0 a) a0a0 a1a1 a2a2 a3a3 y1y1 y2y2 y3y3 y 3,y 4 1 x1x1 x1x1 x1x1 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 This is a trivial algorithm that permits to count the number of ones in any input binary vector (see the signal in vector on the next slide. The RFSM has 2 inputs x 1, x 2 and 4 outputs y 1,…, y 4, where x 1 is equal to 1 when all bits of the vector in_vector have been tested, x 2 is a value of the selected bit of the vector, y 1 copies the result of calculation to the circuit output (see the signal result on the next slide), y 2 resets the datapath counters count_ones and tmp, y 3 and y 4 increment the counters tmp and count_ones correspondingly.

20. Begin y1y1 y2y2 x1x1 x2x2 End 1 1 0 0 y 3,y 4 y3y3 a0a0 a1a1 a2a2 a3a3 a4a4 dummy state a0a0 a) process(clk,rst) variable tmp,count_ones : integer range 8 downto 0; begin if rst = '1' then count_ones := 0; tmp := 0; elsif falling_edge(clk) then if y1 = '1' then result <= conv_std_logic_vector(count_ones,4); end if; if y2 = '1' then count_ones := 0; tmp := 0; end if; if y3 = '1' then tmp := tmp+1; end if; if y4 = '1' then count_ones := count_ones+1; end if; if tmp > 7 then x1 <= '1'; else x1 <= '0'; x2 <= in_vector(tmp); end if; end process; a0a0 a1a1 a2a2 a3a3 y1y1 y2y2 y3y3 y 3,y 4 1 x1x1 x1x1 x1x1 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 x1x2x1x2 b) c) WE Output RAM WE MRAM2 WE MRAM1 WE LRAM2 WE LRAM1 4 bits DATA Y X { y 1,y 2, y 3,y 4 } { x 1,x 2 } RFSM datapath d) write enable for output RAM write enable for the second MUX RAM write enable for the first MUX RAM write enable for the second level RAM write enable for the first level RAM Data