1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 11 Reduced Instruction Set Computing

2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline RISC RationaleRISC Rationale Instruction SetsInstruction Sets Instruction PipelinesInstruction Pipelines Register WindowsRegister Windows Instruction Pipeline ConflictsInstruction Pipeline Conflicts RISC vs. CISCRISC vs. CISC Itanium MicroprocessorItanium Microprocessor

3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speeding Up Typical Code 100% of instructions @ 20 ns100% of instructions @ 20 ns

4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speeding Up Typical Code 100% of instructions @ 20 ns100% of instructions @ 20 ns 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns

5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speeding Up Typical Code 100% of instructions @ 20 ns100% of instructions @ 20 ns 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)

6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speeding Up Typical Code 100% of instructions @ 20 ns100% of instructions @ 20 ns 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c) 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c

7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speeding Up Typical Code 100% of instructions @ 20 ns100% of instructions @ 20 ns 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns98% of instructions @ 18 ns and 2% of instructions at 3 * 18 ns 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c) 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c 20  18.7220  18.72

8. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Fixed-length instructionsFixed-length instructions

9. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Fixed-length instructionsFixed-length instructions Limited loading and storing instructionsLimited loading and storing instructions

10. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Fixed-length instructionsFixed-length instructions Limited loading and storing instructionsLimited loading and storing instructions Fewer addressing modesFewer addressing modes

11. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Fixed-length instructionsFixed-length instructions Limited loading and storing instructionsLimited loading and storing instructions Fewer addressing modesFewer addressing modes Instruction pipelineInstruction pipeline

12. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Fixed-length instructionsFixed-length instructions Limited loading and storing instructionsLimited loading and storing instructions Fewer addressing modesFewer addressing modes Instruction pipelineInstruction pipeline Large number of registersLarge number of registers

13. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Hardwired control unitHardwired control unit

14. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Hardwired control unitHardwired control unit Delayed loads and branchesDelayed loads and branches

15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Hardwired control unitHardwired control unit Delayed loads and branchesDelayed loads and branches Speculative execution of instructionsSpeculative execution of instructions

16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Hardwired control unitHardwired control unit Delayed loads and branchesDelayed loads and branches Speculative execution of instructionsSpeculative execution of instructions Optimizing compilersOptimizing compilers

17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Characteristics Hardwired control unitHardwired control unit Delayed loads and branchesDelayed loads and branches Speculative execution of instructionsSpeculative execution of instructions Optimizing compilersOptimizing compilers Separate instruction and data streamsSeparate instruction and data streams

18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Instruction Sets Fewer instructionsFewer instructions

19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Instruction Sets Fewer instructionsFewer instructions Executed in one clock cycleExecuted in one clock cycle

20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Instruction Sets Fewer instructionsFewer instructions Executed in one clock cycleExecuted in one clock cycle Orthogonal, but not too orthogonalOrthogonal, but not too orthogonal –A OR B = NOT((NOT A) AND (NOT B)) –A XOR B = (A AND (NOT B)) OR ((NOT A) AND B)

21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 MIPS 4000 Instruction Types

22. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 SPARC Instruction Formats

23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

26. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipelines

29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipeline Advantages Reduced hardwareReduced hardware Reduced clock periodReduced clock period Reduced complexity of memory interfaceReduced complexity of memory interface

30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Pipeline Clock Rate Limited by slowest stageLimited by slowest stage Speedup:Speedup: Example:Example:

31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Windowing Global RegistersGlobal Registers Windowed RegistersWindowed Registers Window Data RegisterWindow Data Register Window Pointer RegisterWindow Pointer Register

32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Windowing

33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Windowing

34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Windowing

35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Windowing

36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Register Renaming Arbitrary registers instead of fixed windowsArbitrary registers instead of fixed windows More flexible, but harder to controlMore flexible, but harder to control

37. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Pipeline Conflicts Data conflictsData conflicts Branch conflictsBranch conflicts

38. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Data Conflicts

39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Data Conflicts

40. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 No-op Insertion

41. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 No-op Insertion

42. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering

43. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering

44. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering Not always possibleNot always possible

45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Stall Insertion

46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Stall Insertion

47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Data Forwarding

48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Data Forwarding

49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Data Forwarding

50. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Conflicts

51. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Conflicts

52. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 No-op Insertion

53. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 No-op Insertion

54. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering

55. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering

56. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Conditional Branches

57. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 No-op Insertion

58. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering Ignoring the data conflict:Ignoring the data conflict:

59. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering Ignoring the data conflict:Ignoring the data conflict:

60. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Instruction Reordering Ignoring the data conflict:Ignoring the data conflict: Not always possible to reorder instructions - sometimes must resort to no-op insertionNot always possible to reorder instructions - sometimes must resort to no-op insertion

61. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Annulling

62. Annulling

63. Branch Prediction

64. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Advantages Simpler control unitsSimpler control units

65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Advantages Simpler control unitsSimpler control units Can run at higher clock frequenciesCan run at higher clock frequencies

66. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Advantages Simpler control unitsSimpler control units Can run at higher clock frequenciesCan run at higher clock frequencies More chip space for registersMore chip space for registers

67. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Advantages Simpler control unitsSimpler control units Can run at higher clock frequenciesCan run at higher clock frequencies More chip space for registersMore chip space for registers Easier to incorporate parallelismEasier to incorporate parallelism

68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RISC Advantages Simpler control unitsSimpler control units Can run at higher clock frequenciesCan run at higher clock frequencies More chip space for registersMore chip space for registers Easier to incorporate parallelismEasier to incorporate parallelism Simpler compilersSimpler compilers

69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CISC Advantages Complexity doesn’t always increase costComplexity doesn’t always increase cost Can incorporate previous designsCan incorporate previous designs Backward compatibilityBackward compatibility

70. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Itanium Microprocessor

71. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Itanium Microprocessor IA-64 ISAIA-64 ISA Explicitly Parallel Instruction ComputingExplicitly Parallel Instruction Computing PredicationPredication Speculative ExecutionSpeculative Execution

72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Predication

73. Predication

74. Speculative Execution

75. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speculative Execution

76. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary RISC RationaleRISC Rationale Instruction SetsInstruction Sets Instruction PipelinesInstruction Pipelines Register WindowsRegister Windows Instruction Pipeline ConflictsInstruction Pipeline Conflicts RISC vs. CISCRISC vs. CISC Itanium MicroprocessorItanium Microprocessor