1. Evaluating Logic Resources Utilization in an FPGA-Based TMR CPU
Ricardo Jasinski, Volnei A. Pedroni.
Federal Center of Technological Education of Parana – CEFET/PR
Curitiba-PR, Brazil.
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2. 1. Topics Introduction Traditional TMR The original CPU Implementation
Combinational logic
Sequential logic
Memory circuits
Combinational logic with enable inputs
The original CPU
Implementation
CPU building blocks
Adaptation process
Resources Usage Estimation
Experimental Results
Conclusions
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3. 1. Introduction
Triple modular redundancy (TMR) design techniques add reliability to a system at the expense of extra hardware resources;
In a TMR system, all protected modules must be triplicated, in order to allow for automatic fault masking;
An intuitive conclusion is that the resulting design would require approximately three times as many resources as the original design; however, practical results tend to present a much greater ratio.
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4. 2. Traditional TMR (1/6)
Xilinx, Inc.  design techniques for the implementation of fault- and radiation-tolerant designs;
Basic concepts of TMR:
triplication of the module to be protected;
use of a majority voter:
shortcoming: reliability cannot be grater than that of the voter.
Truth table:: A B C Y 1
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5. 2. Traditional TMR (2/6)
In traditional systems, reliability of the voter can be greater than the reliability of redundant modules;
In an FPGA, voters are usually implemented with the same logic resources than the rest of the circuit;
Solution: triplication of voting circuits
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6. (a) original circuit (no TMR)
2. Traditional TMR (3/6)
Combinational Logic
at any time, outputs depend on the inputs only;
also includes circuits in which the result take more than one clock cycle to be computed;
protection method => simple triplication
no voter needed right after module outputs
Conclusion: purely combinational logic requires no change in original source files; simply create a new, TMR module and instantiate 3 times the original module.
(a) original circuit (no TMR)
(b) protected circuit
(with TMR)
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7. (a) original circuit (no TMR)
2. Traditional TMR (4/6)
Sequential Logic
requires additional care to avoid error persistence
correct TMR implementation:
triplicate all circuits, including combinational logic and flip-flops;
insert one voter circuit in each feedback path.
Conclusion: sequential modules require changes in original source code. In addition, voters must be added within the new TMR entity.
(a) original circuit (no TMR)
(b) protected circuit (with TMR)
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8. 2. Traditional TMR (5/6) Memories
must have a means to avoid error build-up;
application-independent protection techniques are preferable;
FPGAs with dual-port RAMs:
1 port for user application;
1 port for automatic refresh.
(a) original memory circuit (without TMR)
(b) protected memory circuit (with TMR and automatic refresh)
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9. (a) original flip-flop
2. Traditional TMR (6/6)
Combinational Logic with Enable Input
registers may have to maintain stored data for arbitrarily long time periods (application-dependent);
flip-flop adapted for automatic refresh at each clock cycle:
(a) original flip-flop
(b) protected flip-flop
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10. 3. The Original CPU (1/1) Xilinx PicoBlaze;
8-bit CPU, designed for implementation in CPLD and FPGA devices;
Indicated for aplications requiring a complex, but non-time-critical state machine;
4 different configurations;
49 16-bit instructions; eight 8-bit registers.
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11. 3. The Original CPU (2/2) Chosen configuration: for CPLD devices;
Device-independent VHDL code.
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12. 4. Implementation (1/2) Each building block was protected by TMR;
All protected modules were instantiated to create a TMR version of the CPU;
Emphasis on source code reuse;
Systematic changes;
Not necessary to know details on how the adapted circuit works; only information necessary is the kind of logic implemented by each block.
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13. 4. Implementation (2/2)
First step: identification of the CPU`s building blocks;
Second step: application of traditional TMR design techniques;
Third step: evaluation.
Pure Combinational Logic:
picoblaze.vhd, arithmetic.vhd, interrupt_capture.vhd, IO_strobe_logic.vhd, logical_bus_processing.vhd, register_and_flag_enable.vhd, shift_rotate.vhd, zero_flag_logic.vhd.
Combinational Logic with Enable Inputs:
carry_flag_logic.vhd, interrupt_logic.vhd, zero_flag_logic.vhd.
Sequential Logic:
program_counter.vhd, stack_counter.vhd, T_state_and_Reset.vhd.
Memories:
register_bank.vhd, stack_ram.vhd.
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14. 5. Resources Usage Estimation
Estimated resources usage:
Type of Logic
Number of Registers
Number of Logic Cells
Combinational
NRTMR = NR  3
LCTMR = LC  3
Combinational with enable
LCTMR = (LC + NFF)  3 (mín.)
Sequential
LCTMR = (LC + NSE)  3
Memory
NRTMR = (NR + log2M)  3
---
Where
NR = number of registers of the original module
NRTMR = number of registers of the TMR module
M = number of memory positions
LC = number of logic cells of the original module
LCTMR = number of logic cells of the TMR module
NFF = number of flip-flops with enable input
NSE = number of state storage elements
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15. 6. Results (1/2) Table 1 - Synthesis results × estimated values:
Module
Registers
Logic Cells
Original
Estimated
With TMR
arithmatic 9 27 81
carry_flag_logic 1 3 4 15
interrupt_capture 2 6
interrupt_logic 5 24 30
IO_strobe_logic
logical_bus_processing 8
program_counter 52
180
register_and_flag_enable
register_bank 64
201
146 --
813
T_state_and_Reset 12
shift_rotate 16 48
zero_flag_logic 18
stack_counter 21
stack_ram 40
126
351
picoblaze (at entity level) 57
171
Total
155
480
390
1794
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16. 6. Results (2/2)
Table 2 - Increase in resources usage by type of logic:
Type of Logic
Registers
Logic Cells
Without TMR
With TMR
Ratio
Pure Combinational 33 99
3.0
118
354
Combinational w/ Enable 5 15 14 63
4.5
Sequential 13 39 60
213
3.5
Memory
104
327
3.1
198
1164
5.9
Total
155
480
390
1794
4.6
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17. 7. Conclusions
A methodology was proposed, employed and verified, for the adaptation of an existing CPU (or any other circuits) in order to create a TMR version; it is not necessary to know exactly how the adapted circuit works, only the kind of logic implemented in each block;
Traditional TMR design techniques were applied, and the impact in the logic resources usage was recorded, considering the type of logic implemented;
The practical results achieved were greater (more area-consuming) than the intuitively expected values (4.6  ~3.0);
A method for the calculation of logic resources needed in the adaptation of an existing circuit to TMR has also been presented and verified.
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