1. Menu Navigation Presented by: Tzahi Ezra Advisors: Moshe Porian Netanel Yamin One semester project Presented on: 20.10.2015 Project initiation: NOV 2014 PROJECT’S FINAL PRESENTATION

2. Contents  Abstract  Project Goals  Top Architecture  General flow  Micro architecture  Mechanism of use  Testability  Synthesis  Place & route  Problems and solutions  Summary

3. Mobile-phones Military Remote Diagnostic Electronic Flight Abstract  Nowadays, navigation between symbols (icons) in a menu on display screens is a very common operation.  Therefore, it is crucial to enable fast changes to the display.  Implementation using HW only, without SW use, is the common way, in order to minimize frame transmission time and save resources.

4. Project’s goal  Navigation in a menu:  Implement blocks in FPGA, coded in Vhdl HDL, for Moving a cursor symbol right, left, up or down on display screen using HW only:  Receive direction signals from slide switches on the DE2 board  Apply to an internal navigator block, which saves the cursor symbol location  Use the symbol generator project platform with modifications to dispatch the cursor symbol onto the screen  Move the cursor symbol on the screen using the switches and only when the frame starts being drawn from upper left corner  The top level blocks communicate via Wishbone protocol  The project focuses on one of the top level blocks - added internal block and modifications into it

5. Top Architecture reused Navigator

6. General flow Ram initialization: Navigator

7. SDRAM initialization : Navigator General flow

8. Navigator General flow Continuous use:

9. Micro architecture Display controller block Navigator

10. Micro architecture SG TOP: The “brain” block Navigator Inversion

11. To manager Navigator x_y_ location _top Micro architecture Navigator block x_y_ location update_ upon_ vsync Debouncer clk reset right left up down vsync x_out y_out hor_loc ver_loc right_trig left_trig up_trig down_trig x_updated y_updated

12. Manager Micro architecture Manager block select 0101 sym_loc sym_row sym_col reset clk sdram_data[7:0] ver_loc hor_loc inversion sdram_mux_out[7:0] Clk ver_loc hor_loc 1 10 0001010 sdram_mux_out[7:0] 1110101 sym_col sym_row 10 1 0 …2 0001010 FSM Fifo A Fifo B … … … … … … Comparator select 0 1 … 0 1 sdram_data[7:0] 0001010 1110101 0001010

13. Sdram read address = Bank(2) & Ram data out(13) & ‘0’/’1’ & inside row*16(8)/(inside row-16)*16(8) RAM Ram data outSymbol add.Ram rd add. 0000000000000 Add. Of symbol (0,0) in the SDRAM 0 0000000000010 Add. Of symbol (0,1) in the SDRAM 1 ……… 0111111111111 Add. Of symbol (0,19) in the SDRAM 19 … … … 0111111111111 Add. Of symbol (14,19) in the SDRAM 299 SDRAM Symbol row 15 (32) … Symbol row 1 (32) Symbol row 0 (32) 311610 0x CD … 0x CD 0x CD … 0x DF 0x FF 0x AB … 0x BB 0x AB 0x CD … 0x CD 0x CD 0x CD 0x CD 0x CD 0x CD 0x CD 0x CD … 0x CD 0x CD … 0x AB 0x CA 0x CD … 0x CD 0x AC 0x CD … 0x CD 0x CD … 0x AB 0x CA 0x CD … 0x CD 0x CD ……… ……… 0x CD … 0x CD 0x CD … 0x AB 0x CA 0x CD … 0x CD 0x 14 0x 17 … 0x CD 0x CD … 0x AB 0x CA 0x CD … 0x CD 0x CD 14…0…0…0 Symbol row(X) 19…0 …1…0 Symbol column(Y) 31…10…0…0 Inside row 0…0…0…0 Vertical location …1…1…1 Horizontal location …1…1…0 Ram read address 00011111 11111111 11110000 … 000000 000000 000000 100000 00011111 11111110 00000000 … 00000000 00000100 00000000 … 00000000 00000000 00000000 Sdram read address 0x17 … 0xDF0x14 … 0x52 … 0xBB0xAB Sdram_mux_out Ram read address = 20*X+Y Symbol 0 Symbol 1 Symbol 4095 … Micro architecture Memories Match occurs… Selected row Inversion occurs

14. Mechanism of use Navigation : downupleftright Next stateCurr. state YXYXYXYXYX 10141 190100 1 14001810019 01813191418001419 0 130 19141 0 1X X+10X-10X+101..18 19Y+119Y-1 18Y+101..1319 0X-113X14X-114X+1141..18 Y+10Y-10 19Y11..130 Y+1XY-1XYX-1YX+11..131..18 Vsync arrives… … Indicates when the frame starts being drawn from upper left corner Upper row Upper right corner Lower left corner

15.  Simulation using ModelSim  Unit level and top level tests  Testing using randomization in different aspects:  Direction selection  Switching time  Interval time  Examine the results using assert statements, for a better control  Lab examination  Response of the cursor symbol to switches movements  Special scenario when located in edges of the frame  Response of the cursor symbol to reset button  Symbol inversion in cursor symbol coverage Testability Test plan:

16. TOP SYNTHESIS TB TOP SYNTHESIS TOP SYNTHESIS Uart_tx_ gen global_nets _top uart_serial_in clk Fpga_clk reset Fpga_rst uart transmission file, MDS TOP vesa clk, sdram clk, system clk and reset RX path TX path SDRAM Controller Mem management Display Controller SDRAM Model RGB debug purposes Testability Top level test structure:

17. Waveform example: Testability Navigation operation, Navigator block: Time interval to trigger a change after switching begins, is set to 50 ns vsync arrival, after 660 ns of down switching Down switching while cursor’s vertical location is 1

18. I’ve used checkers in order to better control the simulation: If the assert condition would have been FALSE (assert (dout = ‘1’)), than the report clause would have been transmitted to the console, with the mentioned severity: Testability Checkers use:

19. Waveform example: Testability Pixel inversion,Top level block:

20. Waveform example: Testability Pixel inversion,Top level block

21. Testability Lab examination down up left right reset System view:

22. Testability Lab examination Symbol addition: Cursor symbol

23. Testability Lab examination Cursor navigation to symbol in location (12,3): Cursor symbol inverts original symbol

24. Synthesis Precision rtl view:

25. Place & route Quartus tool resources report:

26. 1. Problem: updating the cursor symbol's location after the frame has started being drawn, might cause pixel smearing.  Solution: updating the cursor symbol's location immediately after vsync arrival, action that is performed in the update_upon_vsync block, guarantees that the cursor symbol will not change its location in the middle of a frame. Problems and solutions

27. 2. Problem: the system clock (100 MHz) did not appeared in the clock path, therefore caused timing problems.  Solution: using quartus Technology Map viewer, I've noticed that the fpga clock (50 MHZ) was mistakenly connected as the system clock. Problems and solutions

28. 3. Problem: synchronization problem of the system clock(100 MHz) with the update_upon_vsync block. The rise of the system clock did not trigger the event of location update, but the vsync signal. That caused this block to be asynchronous and might cause timing problems.  Solution: the system clock was added to the architecture synchronous part so that the location would be updated when the vsync signal is set to ‘1’ only in the rising edge of the clock. Problems and solutions

29.  The main goal of this project, navigating between symbols using a cursor symbol, adding blocks to the symbol generator project platform, while managing to fulfill the timing constrains, simulating and debugging VHDL code using ModelSim program, synthesizing using precision tool and P&R using Quartus program was done successfully  Moreover, goal had been achieved by:  Organized working methods using the SVN and google drive cloud storage, helped synchronizing with the project's supervisors.  Use of randomization while testing  Proper use of Precision and Quartus capabilities, such as Technology Map viewer.  Documentations – helped organization and eased the block design and the system understanding. Summary

30. The END Lets continue to the lab