2. بنام خدا ريز پردازنده ها Microprocessors

3. Reference Books منابع : v Title: The Z80 Microprocessor, Hardware, Software, programming & interfacing v Author: Barry B. Brey v Translator: Hossein Nia v Publisher: Astane Ghodse Razavi ( Beh Nashr )

4. Reference Books منابع : v Z80 Family DATABOOK v Publisher: ZILOG Corp. v Copyright 2004

5. Introduction مقدمه : v Microprocessor / (uP) / (MPU) u A uP is a CPU on a single chip. u Components of CPU ALU, instruction decoder, registers, bus control circuit, etc. v Micro-computer (u-Computer) u small computer u uP + peripheral I/O + memory specifically for data acquisition and control applications v Microcontroller (uC) u u-Computer on a single chip of silicon

6. uP vs. uC ريزپردازنده و ريزكنترلر : v A uP u Only is a single-chip CPU u Bus is available u RAM capacity u ROM is smaller than RAM (usually) u number of I/O ports is selectable A uC u Contains a CPU and RAM,ROM,Peripherals, I/O ports in a single IC u Internal hardware is fixed u Communicate by port u ROM is larger than RAM (usually) u Small power consumption u Single chip, small board u Implementation is easy u Low cost

7. uP vs. uC – cont. ريزپردازنده و ريزكنترلر : v Applications: u uCs are suitable to control of I/O devices in designs requiring a minimum component u uPs are suitable to processing information in computer systems

8. uP vs. uC – cont. ريزپردازنده و ريزكنترلر : v uC is easy to use and design. u Only single chip can be a complete system u interfacing to other devices, for example, motors, displays, sensors, and communicate with PC. v In contrast, similar system that builds from uP would require a lot of additional units, u such as RAM, UART, I/O, TIMER and etc.

9. uC is a Reusable Hardware ريزكنترلر قابل برنامه ريزي مجدد است : v Logic circuit provides limited function for one single design. In order to change circuit’s functionality, we need to redesign the circuits. v uC can reprogram and change functionality of every port, input to output or digital to analog on the fly.

10. uCs v Many uCs are existing right now. u 8051, 68HC11, MSP430, ARM series, and etc. v We may widely divide it with how it is designed u RISC/CISC architecture. v What is the main difference between RISC/CISC? v Does it make any difference to our application?

11. The Microprocessor (MPU) v The uP is the ‘ brain of the microcomputer ’ v Is a single chip which is capable of u processing data u controlling all of the components which make up the microcomputer system v µP used to sequence executions of instructions that is in memory v uP Fetch, Decode, and Execute the instruction v The internal architecture of the microprocessor is complex.

12. The Microprocessor (MPU) v microprocessor (MPU) typically contains u Registers: Temporary storage locations for program instruction or data. u The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operations u Timing and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence

13. Microcomputers ريزكامپيوترها : v All Microcomputers consist of (at least) : u 1. Microprocessor Unit (MPU) u 2. Program Memory (ROM) u 3. Data Memory (RAM) u 4. Input / Output ports u 5. Bus System u (and Software) v MPU is the brain of microcomputer

14. Parts of a Computer CPU control ALU MemoryI/O Instruct. data bus

15. System Architecture CPU Memory Bus I/O ports I/O devices

16. Microcomputers ريزكامپيوترها :

17. The Input/Output (I/O) System ورودي / خروجي : v I/O is the link between the MPU and the outside world. v An input port is a circuit through which an external device can send signals (data?) to the MPU. v An output port is a circuit that allows the MPU to send signals (data?) to external devices. v I/O ports connect both digital and analogue devices by DAC and ADC

18. Bus گذرگاهها ( مسيرهاي عمومي ): v A Bus is a common communications pathway used to carry information between the various elements of a computer system v The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another v The individual subsystems of the digital computer are connected through an interconnecting BUS system

19. Bus گذرگاهها ( مسيرهاي عمومي ): v There are three main bus groups u ADDRESS BUS u DATA BUS  CONTROL BUS

20. Data Bus گذرگاه داده : v The Data Bus carries the data which is transferred throughout the system. ( bi-directional) v Examples of data transfers u Program instructions being read from memory into MPU. u Data being sent from MPU to I/O port u Data being read from I/O port going to MPU u Results from MPU sent to Memory v These are called read and write operations

21. Address Bus گذرگاه آدرس : v An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer v The Address Bus is used to transmit the address of the location to the memory or the I/O port. v The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.

22. Control Bus گذرگاه كنترل : v The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components. v Control signals are unidirectional, and are mainly outputs from the MPU. v Example Control signals u RD: read signal asserted to read data into MPU u WR: write signal asserted to write data from MPU

23. Main memory حافظه اصلي : v The duties of the memory are : u To store programs u To provide data to the MPU on request u To accept result from the MPU for storage v Main memory Types u ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) u RAM : random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values

24. Read-Only Memory حافظه فقط خواندني : v uP can read instructions from ROM quickly v Cannot write new data to the ROM v ROM remembers the data, even after power cycled v Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )

25. Available ROMs : ROM انواع v Masked ROM or just ROM v PROM or programmable ROM (once only) v EPROM (erasable via ultraviolet light) v Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading)  EEPROM (electrically erasable read-only memory, also known as EEROM—both reading and writing are very slow but can program millions of times…useless for storing a program but good for say configuration information.

26. .. ROM A0 A1 A2 Am D0 Dn D1 D2 n+1 bit Data Capacity : m+1 bit Address : Output Enable connect to RD of uP : Chip Enable to Address decoder ROM PROM EEPROM

27. v.v. Timing Diagram for a Typical ROM A0-Am D0-Dn OE falls to data valid Addr. valid to data valid

28. v.v. 27XX EPROM 16 kbit 2 kbyte 32 kbit 4 kbyte 64 kbit 8 kbyte PGM and VPP are used to programming

29. 27XXX EPROM 128 kbit 16 kbyte 256 kbit 32 kbyte 512 kbit 64 kbyte 1024 kbit 128 kbyte

30. 256 kbit 32 kbyte 64 kbit 8 kbyte 1026 kbit 128 kbyte 4096 kbit 512 kbyte 16 kbit 2 kbyte 28XX E2PROM

31. RAM (Random Access Memory) حافظه خواندني / نوشتني : v The uP can read the data from RAM quickly, v The uP can write new data quickly to RAM v RAM forgets its data if power is turned off v Two type of is available : u Static RAM(SRAM): ff base, fast, expensive, low cap / vol, applied for cache, no refresh. u Dynamic RAM (DRAM): cap base, slow, low cost high capacity/volume, applied for main memory(pc) need refresh.

32. RAM(Static) A0 A1 A2 Am D0 Dn D1 D2 n+1 bit Data Capacity : m+1 bit Address : Chip Select to Address decoder RAM : Read signal connect to MemRD of uP : Write signal connect to MemWR of uP Data bus is Bidirectional

33. Session 2 v Microprocessors v History v Data width v 8086 vs 8088 v 8086 pin description v Z80 Pin description

34. Microprocessors v Microprocessors come in all kinds of varieties from the very simple to the very complex v Depend on data bus and register and ALU width uP could be 4-bit, 8-bit, 16-bit, 32-bit, 64-bit v We will discuss two sample of it u Z80 as an 8-bit uP u and 8086/88 as an 16-bit uP v All uPs have u the address bus u the data bus u RD, WR, CLK, RST, INT,...

35. History تاريخچه : Company4 bit8 bit16 bit32 bit64 bit Intel 4004 4040 8008 8080 8085 8088/6 80186 80286 80386 80486 80860 Pentium ZilogZ80 Z8000 Z8001 Z8002 Motorola 6800 6802 6809 68006 68008 68010 68020 68030 68040

36. Internal and External Bus v Internal bus is a pathway for data transfer between registers and ALU in the uPs v External bus is available externally to connect to RAM, ROM and I/O v Int. and Ext. Bus width may be different v For example u In 8088 Int. Bus is 16-bit, Ext. bus is 8-bit u In 8086 Int. Bus is 16-bit, Ext. bus is 16-bit

37. 8086 vs 8088 16_bit Data Bus 20_bit Address 8_bit Data Bus 20_bit Address 8088 8086 Only external bus of 8088 is 8-bit

38. 8086 Pin Assignment نام پايه ها :

39. 8086 Pin Description تشريح پايه ها : Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground AD0..AD7, A8..A15, A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX’ (input) : Indicates Operating mode READY (input, Active High) : take uP to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately terminate its present activity. TEST’ (input, Active Low) : Connect this to HIGH HOLD (input, Active High) : Connect this to LOW HLDA (output, Active High) : Hold Ack INTR (input, Active High) : Interrupt request INTA’ (output, Active Low) : Interrupt Acknowledge NMI (input, Active High) : Non- maskable interrupt

40. 8086 Pin Description DEN’ (output) : Data Enable. It is LOW when processor wants to receive data or processor is giving out data (to 74245 ) DT/R’ (output) : Data Transmit/Receive. When High, data from uP to memory When Low, data is from memory to uP (to74245 dir) IO/M’ (output) : If High uP access I/O Device. If Low uP access memory RD’ (output) : When Low, uP is performing a read operation WR’ (output) : When Low, uP is performing a write operation ALE (output) : Address Latch Enable, Active High Provided by uP to latch address When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines

41. Z80 CPU Pin Assignment : Z80 پايه هاي

42. Z80 Pin Description A15-A0 : Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus. D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts. RD: Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.

43. Z80 Pin Description MREQ Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 IORQ Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1 M1 Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM

44. Z80 Pin Description  INT  Interrupt Request (input, active Low).  Interrupt Request is generated by I/O devices.  Checked at the end of the current instruction  If flip-flop (IFF) is enabled.  NMI  Non- Maskable Interrupt  (Input, negative edge-triggered).  Higher priority than INT.  Recognized at the end of the current Instruction  Independent of the status of IFF  Forces the CPU to restart at location 0066H.

45. Z80 Pin Description  BUSREQ  Bus Request (input, active Low).  higher priority than NMI  recognized at the end of the current machine cycle.  forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp.  BUSACK  Bus Acknowledge (output, active,Low)  indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high-impedance states.

46. Z80 Pin Description RESET Reset (input, active Low). RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive state. must be active for a minimum of three full clock cycles before the reset operation is complete.

47. بلوك دياگرام Z80 Z80 CPU

48. Z80 Programming Model

49. Register Set مجموعه ثبات ها : v A : Accumulator Register v F : Flag register v Two sets of six general-purpose registers u may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’) u or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’) v The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: u EXX (BC) (BC'), (DE) (DE'), (HL) (HL') u EX AF, AF ’ (AF) (AF') what is this instruction useful for?

50. Register Set(cont) v 4 16-bit registers hold memory address (pointers) u index registers (IX) and (IY) are 16-bit memory pointers u 16 bit stack pointer (SP) u Program counter (PC) v Program counter (PC) u PC points to the next opcode to be fetched from ROM u when the µP places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location v Special purpose registers u I : Interrupt vector register. u R : memory Refresh register

51. Flag Register ثبات پرچم ها : SSign Flag (1:negativ)* ZZero Flag (1:Zero) HHalf Carry Flag (1: Carry from Bit 3 to Bit 4)** PParity Flag (1: Even) VOverflow Flag (1:Overflow)* NOperation Flag (1:previous Operation wassubtraction)** CCarry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand) *:2-complement number representation **:used in DAA-operation for BCD-arithmetic

52. DAA - Decimal Adjust Accumulator before DAAafter DAA OpNCBits 4-7HBits 0-3A=A+..C ADD ADC 000-90 000 000-80A-F060 000-910-3060 00A-F00-9601 009-F0A-F661 00A-F10-3661 010-200-9601 010-20A-F661 010-31 661 SUB SBC NEG 100-90 000 100-816-FFA0 117-F00-9A01 116-F1 9A1 Adjusts the content of the Accumulator A for BCD addition and subtraction operations such as ADD, ADC, SUB, SBC, and NEG according to the table:

53. Instruction cycles, machine cycles and “T-states” v Instruction cycle is the time taken to complete the execution of an instruction v Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. v T-state = 1/f (f:Z80 Clock Frequency) u f= 4MHZ  T-state=0.25 uS

54. Basic CPU Timing Example

55. Opcode Fetch Bus Timings (M1 Cycle)

56. The R register v Is increased at every first machine cycle (M1). v Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same v Bit 7 can be changed using the LD R,A instruction. v LD A,R and LD R,A access the R register after it is increased v R is often used in programs for a random value, which is good but of course not truly random. the block instructions decrease the PC with two, so the instructions are re-executed.

57. Memory read/write cycle

58. Adding One Wait State to an M1 Cycle

59. Adding One Wait State to Any Memory Cycle

60. IO read/write cycle During I/O operations a single wait state is automatically inserted

61. Bus Request/Acknowledge Cycle

62. Interrupt Request/Acknowledge Cycle Two wait states are automatically added to this cycle

63. Non - Maskable Interrupt Request Operation

64. M1 Refresh Cycle v Takes 4T to 6Ts v Z80 includes built in circuitry for refreshing DRAM v This simplifies the external interfacing hardware v DRAM consists of MOS transistors, which store Information as capacitive charges; each cell needs to be periodically refreshed v During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refresh

65. Wait Signal v the Z80 samples the wait signal during T2 if low then Z80 adds wait v states to extend the machine cycle v used to interface memories with slow response time v Slow memory is low cost

66. There are two types of interrupts: v non mask-able (NMI) u Could not be masked u Jump to 0066H of memory v mask-able(INT) u Has 3 mode u Can be set with the IM x Instruction u IM 0 sets Interrupt mode 0 u IM 1 sets Interrupt mode 1 u IM 2 sets Interrupt mode 2 وقفه ها : Interrupts

67. Interrupt Modes حالت هاي وقفه : v Mode 0: u An 8 bit opcode is Fetched from Data BUS and executed u The source interrupt device must put 8 bit opcode at data bus u 8 bit opcode usually is RST p instructions v Mode 1: u A jump is made to address 0038h u No value is required at data bus v Mode 2: u A jump is made to address (register I × 256 + value from interrupting device that puts at bus) u I is high 8 bit of interrupt vector u Value is low 8 bit of interrupt vector

69. Z80 CPU Instruction Description v 158 different instruction types v Including all 78 of the 8080A CPU. v Instruction groups u Load and Exchange u Block Transfer and Search u Arithmetic and Logical u Rotate and Shift u Bit Manipulation (Set, Reset, Test) u Jump, Call, and Return u Input/Output u Basic CPU Control

70. Addressing Modes v Immediate v Immediate Extended v Modified Page Zero Addressing (rst p) v Relative Addressing u Jump Relative (2 byte) One Byte Op Code 8-Bit Two’s Complement Displacement (A+2) v Extended Addressing u Absolute jump One byte opcode 2 byte address v Indexed Addressing u (Index Register + Displacement) (IX+d) u 2 byte opcode u 1 byte displacement

71. Addressing Modes (cont.) v Register Addressing u LD C,B v Implied Addressing u Op Code implies other operand(s) u ADD E v Register Indirect Addressing u 16-bit CPU register pair as pointer (such as HL) u ADD (HL) v Bit Addressing u set, reset, and test instructions. u SET 3,A u RES 7,B

72. Minimal Configuration of a Z80 Microcomputer

73. Z80 Memory Connection v CPU 16 bit address bus  64 k memory (max) v CPU 8 bit data bus  8 bit data width v Generally should be connected u Data to Data u Address to Address u WR to WR u RD to RD u MREQ to CS

74. Memory connection (cont.) RAM 64 kb Z80 CPU D7~D0 A15~A0  If only one RAM chip Full size (64 kb capacity)

75. Memory connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15  If RAM capacity was 32 kb  A15 composed with MREQ  RAM area is from 0000h to 7FFFh

76. Memory connection (cont.) v There is two 32 kb RAM v Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. v Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.

77. Memory connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0 A14~A0 A15  There is two 32 kb RAM  A15 applied to select one RAM chip  Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1)

78. Memory connection (cont.) ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0 A14~A0 A15  32 kb ROM and 32 kb RAM  ROM doesn’t have wr signal

79. Memory connection (cont.) Z80 CPU There is 4 memory chip A14 and A15 applied to chip selection

80. Address Bit Map A15 to A0 (HEX) AA 11 54 32 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0000h 3FFFh 00 00 11 0000 1111 0000 1111 0000 1111 ROM 4000h 7FFFh 01 00 01 11 0000 1111 0000 1111 0000 1111 RAM 1 8000h BFFFh 10 00 10 11 0000 1111 0000 1111 0000 1111 RAM 2 C000h FFFFh 11 00 11 0000 1111 0000 1111 0000 1111 RAM 3 Selects chip Selects location within chips

81. Memory Map v Represents the memory type v Address area of each memory chip v Empty area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM 1 16k 8000h BFFFh RAM 2 16k C000h FFFFh RAM 3 16k

82. Memory Map v Empty Area cann’t write and read v Read op. returns FFh value ( usualy ) v Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM 2 C000h FFFFh RAM 3 ROM 16 kb D7~D0 A13~A0 A15 RAM 16 kb D7~D0 A13~A0 RAM 16 kb D7~D0 A13~A0 A14 En S0 S1

83. Memory Map v Empty Area cann’t write and read v Read op. returns FFh value (usualy) v Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM C000h FFFFh Empty ROM 16 kb D7~D0 A13~A0 A15 RAM 16 kb D7~D0 A13~A0 A14 En S0 S1

84. Full and Partial Decoding v Full (exhaust) Decoding u All of the address lines are connected to any memory/device to perform selection u Absolute address : any memory location has one address v Partial Decoding u When some of the address lines are connected the memory/device to perform selection u Using this type of decoding results into roll- over addresses (fold back or shading). u roll-over address : any memory location has more than one address

85. Partial Decoding v A15~A12 has no connection v Then doesn’t play any role in addressing v What is the Memory and Address Bit map? RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12

86. Partial Decoding A15 to A0 (HEX) AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip X000h XFFFh xxxx 0000 1111 0000 1111 0000 1111 RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12 0000h 0FFFh RAM 1000h 1FFFh RAM’ 2000h 2FFFh RAM’ 3000h 3FFFh RAM’ F000h FFFFh RAM’  Every memory location has more than one address  For example first RAM location has addresses:  0000h  1000h  2000h  3000h …………….  F000h Roll-over Address

87. Partial Decoding v A12 only connected to RAM v A13 has no connection v What is the memory map? ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13

88. Partial Decoding v 8 roll-over address for ROM v 4 roll-over address for RAM AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0xxx 0000 1111 0000 1111 0000 1111 ROM X0x0 X0x1 0000 1111 0000 1111 0000 1111 RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13

89. Partial Decoding AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0xxx 0000 1111 0000 1111 0000 1111 4k ROM X0x0 X0x1 0000 1111 0000 1111 0000 1111 8k RAM 0000h 1FFFh RAM’ 0000h 0FFFh ROM 1000h 1FFFh ROM’ 2000h 3FFFh RAM’ 2000h 2FFFh ROM’ 3000h 3FFFh ROM’ 4000h 5FFFh 4000h 4FFFh ROM’ 5000h 5FFFh ROM’ 6000h 7FFFh 6000h 6FFFh ROM’ 7000h 7FFFh ROM’ 8000h 9FFFh RAM F000h FFFFh A000h BFFFh RAM’ C000h DFFFh E000h FFFFh ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13 Conflict

90. Partial Decoding AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0xxx 0000 1111 0000 1111 0000 1111 4k ROM X1x0 X1x1 0000 1111 0000 1111 0000 1111 8k RAM 0000h 1FFFh 0000h 0FFFh ROM 1000h 1FFFh ROM’ 2000h 3FFFh 2000h 2FFFh ROM’ 3000h 3FFFh ROM’ 4000h 5FFFh RAM’ 4000h 4FFFh ROM’ 5000h 5FFFh ROM’ 6000h 7FFFh RAM’ 6000h 6FFFh ROM’ 7000h 7FFFh ROM’ 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM E000h FFFFh RAM’ ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13 Conflict

91. Full (exhaustive) decoding 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 2764 EPROM 8k  8 D7~D0 A12~A0 6116 RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A13 A12 A11 A15 A14 7421 0000h-07FFh 0800h-0FFFh 1000h-17FFh 1800h-1FFFh 2000h-27FFh AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0000 0001 0000 1111 0000 1111 0000 1111 ROM 0010 0000 0111 0000 1111 0000 1111 RAM

92. Partial decoding 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 2764 EPROM 8k  8 D7~D0 A12~A0 6116 RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A15 A14 A13 0000h-1FFFh 2000h-3FFFh AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0000 0001 0000 1111 0000 1111 0000 1111 ROM 001x x000 x111 0000 1111 0000 1111 RAM GND VCC

93. 1 Bit Memory With Separated I/O 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in D0 D1D7 D7-D0 A11-A0

94. What is the memory (addr. bit) map D0 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in D1 D7 D7-D0 A11-A0 2764 EPROM 8k  8 D7~D0 A12~A0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 0000h-1FFFh 2000h-3FFFh A15 A14 A13 GND VCC

95. Adding RAM & ROM

96. Minimum Z80 Computer System

97. Z80-µP-Family (Typical Environment)

98. Z80 Input Output  Z80 at most could have 256 input port and 256 output  8 bit port address is placed on A7–A0 pin to select the I/O device  OUT (n), A  n is 8 bit port address  Content of A is data  OUT (C), r  Content of C is a port address  r is a data register  IN A, (n)  n is 8 bit port address  Data is transferred to A  IN r (C)  Content of Reg C is a port address  Input data is transferred to r (data reg)

99. Remember IO read/write cycle

100. Z80 and simple output port OUT (03), A

101. Z80 and simple input port Z80 CPU A14 A0 : D7 D6 RD IORQ A15 D5 D4 D3 D2 D1 D0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IORD 74LS244 A0 A1 A2 A3 A4 A5 A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1G2 5V IN A, (02)

102. 8088 and simple output port A 1 5 8088 Minimum Mode A18 A0 : D7 D6 IOR IOW A19 D5 D4 D3 D2 D1 D0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IOW 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 OELE

103. 8088 and simple input port A 1 5 8088 Minimum Mode A18 A0 : D7 D6 IOR IOW A19 D5 D4 D3 D2 D1 D0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IOW What is this? 74LS244 A0 A1 A2 A3 A4 A5 A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1G2 5V

104. Simplified Drawing of 8088 Minimum Mode D7 - D0Q7 - Q0 OE LE 74LS373 D7 - D0Q7 - Q0 OE LE 74LS3738088 AD7 - AD0 A15 - A8 A19/S6 - A16/ S3 DEN DT / R IO / M RD WR ALE D7 - D4Q7 - Q4 OE LE 74LS373 D3 - D0Q3 - Q0 GND A7 - A0B7 - B0 E DIR 74LS245 MEMR MEMW IOR IOW A7-A0 A15-A8 A19-A16 D7-D0

105. Minimum Mode 2 20 bytes or 1MB memory 1 MB Memory D7 - D0 A19 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A19 - A0 MEMR MEMW CS

106. What are the memory locations of a 1MB (2 20 bytes) Memory? A19 to A0 (HEX) AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 000000000 FFFFF1111 Example: 34FD0 0011 0100 11111 1101 0000

107. Minimum Mode 512 kB memory 512 kB Memory D7 - D0 A18 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A18 - A0 MEMR MEMW CS A19 What do we do with A19? 1)Don’t connect it 2)Connect to cs What is the difference?

108. 512 kB Memory Map v Don’t connect it u A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it. u A19=0 is the same as A19=1 for Memory v Connect to cs u If A19=0 Memory chip act normal function 00000h 7FFFFh 512k Mem 80000h FFFFFh 512k Mem’ 00000h 7FFFFh 512k Mem 80000h FFFFFh Empty

109. 2  512 kB memory 512 kB RAM1 D7 - D0 A18 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A18 - A0 MEMR MEMW CS A19 MEMR MEMW 512 kB RAM2 D7 - D0 A18 - A0 RD WR MEMR MEMW CS

110. 2  512 kB memory AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip 0000 0111 0000 1111 0000 1111 0000 1111 0000 1111 ROM 1000 1111 0000 1111 0000 1111 0000 1111 0000 1111 RAM 00000h 7FFFFh 512k RAM1 80000h FFFFFh 512k RAM2 What are the memory locations of two consecutive 512KB (2 19 bytes) Memory?

111. Interfacing four 256K Memory Chips to the 8088 Microprocessor 8088 Minimum Mode A17 A0 : D7 D0 : MEMR MEMW A18 256KB #3 A17 A0 : D7 D0 : RD WR CS A19 256KB #2 A17 A0 : D7 D0 : RD WR CS 256KB #1 A17 A0 : D7 D0 : RD WR CS 256KB #4 A17 A0 : D7 D0 : RD WR CS

112. Interfacing four 256K Memory Chips to the 8088 Microprocessor

113. Memory chip#__ is mapped to: AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#3 RAM#4

114. Interfacing several 8K Memory Chips to the 8088  P

115. Interfacing 128 8K Memory Chips to the 8088  P

116. 8088 Minimum Mode A12 A0 : D7 D0 : MEMR MEMW A13 A14 8KB #2 A12 A0 : D7 D0 : RD WR CS 8KB #1 A12 A0 : D7 D0 : RD WR CS 8KB #128 A12 A0 : D7 D0 : RD WR CS A15 A16 A17 A18 A19 : :

117. Memory chip#__ is mapped to: AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#126 RAM#127 RAM#128

118. What is the Memory and Address Bit map? 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1G1 2764 EPROM 8k  8 D7~D0 A12~A0 6116 RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A14 A13 A12 A15 7408 VCC 74244 INPUT