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Reconfigurable FFT architecture

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Presentation on theme: "Reconfigurable FFT architecture"— Presentation transcript:

1 Reconfigurable FFT architecture
Saba Zia Dec 17,2008

2 Specifications 64 point FFT 32 butterfly operations
14 points 2’s complement representation DIF radix-2 LUT for twiddle factors Rounding off for arithmetic gain

3 Fast Fourier Transform - Mathematics

4 Simplified 8-point FFT -1 W0 W1 W2 W3 W4 W5 W6 W7 Time Domain Samples
j -j W0 W1 W2 W3 W4 W5 W6 W7 Time Domain Samples Frequency Outputs

5 Periodicity of twiddle factors

6 DIT and DIF

7 8 point radix 2 FFT - DIF

8 Algorithm Number of points = N = 64 Total stages = log2N = 6
Total butterflies in each stage = N/2 = 32 Twiddle factor to retrieve in each stage = N/2 Optimal retrieval of twiddle factor in each stage = 2(total stages – stage number) First Data index = i (where i = 0 to N/2) Second Data index = 2(total stages – stage number) + i Twiddle Factor index = j = 0 to 2(total stages – stage number) - i

9 State Machine

10 Split radix structure 64-point FFT 64-point FFT 4- point FFT
4- point reorder 64-point FFT 64-point FFT


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