Presentation is loading. Please wait.

Presentation is loading. Please wait.

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Group Research 1 QNoC.

Similar presentations


Presentation on theme: "Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Group Research 1 QNoC."— Presentation transcript:

1 Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Group Research 1 QNoC

2 Hierarchical NoCs Hybrid Ring/Mesh S. Bourduas and, Z. Zilic, “Latency reduction of global traffic in wormhole-routed meshes using hierarchical rings for global routing.” ASAP 2007. ‏ PyraMesh R. Manevich, I Cidon and, A. Kolodny. “Handling global traffic in future CMP NoCs” SLIP 2012. ‏ 2

3 Hierarchical NoCs lower hop distances 3

4 Max. Hop distance vs. Number of Modules 4

5 Parallel link delay model Elmore’s delay: Repeated wire [Bakoglu - 1990]: 5

6 Links delay in 16x16 hierarchical NoC 300 mm 2 die Short 1 mm Medium 1.9 mm Long 3.4 mm 16x16 Mesh. 8x8, 4x4 Upper Levels Elmore’s Delay – Unrepeated, min. size global links (ITRS): 29 nm Technology Short: 0.11ns Medium: 0.41ns Long: 1.31ns 12X ~17mm 6

7 Adjusting delay of parallel links Wire sizing: Lower RC delay by changing wire pitch (S and W). Repeaters insertion: Lower wire delay by inserting repeaters. 7

8 Wire design parameters Λ W – Scaling of W vs. min. size global wire [ITRS]. ParameterRange ΛWΛW [1..50] ΛSΛS ρ[0..10] SRSR [0..1] Λ S – Scaling of S vs. min. size global wire ρ - Density of repeaters per millimeter S R – Repeaters’ size normalized to Bakolu’s optimal size 8

9 Cost of adjusted links Wiring Cost - Power Cost - Unified cost function - W C = 1 W C = 2 Min.Pitch 2X Min. Pitch WE USE 9

10 Finding lowest cost wires for target frequency ParameterRange ΛWΛW [1..50] ΛSΛS ρ[0..10] SRSR [0..1] 1.Shuffle multiple design configurations (Monte-Carlo). 2.For the target frequency, place each configuration on “Cost Function (CF)- Link Length” plane. 3.Lowest cost configurations along the Pareto curve. 10

11 Lowest cost links – 29nm-8nm technology nodes Max. achievable single cycle lengths – 29nm Max. achievable single cycle lengths – 20nm 11

12 Max. achievable link length for different target frequencies 3.4 mm 12

13 Back to our example 1 mm 1.9 mm 3.4 mm 29nm, 17nm, 10nm Technology nodes 1 GHz – 5GHz Target frequencies. Delay of wires at: Cost of adjusting wires to: 13

14 Our example – Delays of NoC wires before adjustements 1 GHz 2 GHz 5 GHz 3 GHz 4 GHz 14

15 Costs of adjusting wires to 1GHz 15 Cost Function (CF) [%] 1 GHz

16 Costs of adjusting wires to 2GHz 2 GHz Cost Function (CF) [%] 16

17 Costs of adjusting wires to 3GHz 3 GHz Cost Function (CF) [%] 17

18 Costs of adjusting wires to 4GHz 4 GHz Cost Function (CF) [%] 18

19 Costs of adjusting wires to 5GHz 5 GHz Cost Function (CF) [%] 19

20 Definition of cost overhead of adjusting long wires In our example (CF = Cost Function, l = length ): long – 3.4mmmed – 1.9mmshort – 1mm 20

21 Total length of each kind of links – our 16x16 NoC 21

22 Cost overhead of adjusting long wires – our 16x16 NoC 65 nm 28 nm 22

23 Conclusions Long links in hierarchical NoCs: Are a minority. 23

24 Thank You! 24

25 Area cost of repeaters 25


Download ppt "Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Group Research 1 QNoC."

Similar presentations


Ads by Google