1. Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics

2. Digital Electronics and Computer Interfacing2 3.7.3 D flip-flop Q D 0 1 0 1 0 1 Timing diagram E 0 1 D Q Q E D Q follows D when the flip-flop is enabled

3. Digital Electronics and Computer Interfacing3 3.7.4 Edge triggered SR flip-flop Two gated SR flip-flops with the second enable line inverted with respect to the first Q Q S R E

4. Digital Electronics and Computer Interfacing4 3.7.4 Edge triggered SR flip-flop Q S E R 0 1 0 1 0 1 0 1 time Timing diagram Falling edge of the enable line triggers change of flip-flop!

5. Digital Electronics and Computer Interfacing5 3.7.5 JK flip-flop The outputs and are feed back to the input gates Q Q J K E Edge triggered flip-flop with no invalid state!

6. Digital Electronics and Computer Interfacing6 3.7.5 JK flip-flop Timing diagram Q J E K 0 1 0 1 0 1 0 1 time

7. Digital Electronics and Computer Interfacing7 Q Q J K Q Q S R 3.7.6 Flip-flop symbols SR flip-flop Circle & triangle indicates high-to-low edge triggered version Enable/clock input Triangle indicates low-to-high edge triggered version JK flip-flop Q Q D D flip-flop Round input indicates that the clock-level causes the transition

8. Digital Electronics and Computer Interfacing8 3.7.7 Flip-flop applications Switch debouncing: +5 V S R Q Q 1k 

9. Digital Electronics and Computer Interfacing9 3.7.7 Flip-flop applications Switch debouncing: +5 V S R Q Q Q S 0 5 V 0 0 Timing diagram R

10. Digital Electronics and Computer Interfacing10 3.7.7 Flip-flop applications Asynchronous counter (ripple counter) Q Q J K 1 Q Q J K 1 Q Q J K 1 Q Q J K 1 LSBMSBABCD E - clock A B C D 1 1 0 1 1 = 11 10 101

11. Digital Electronics and Computer Interfacing11 3.7.7 Flip-flop applications Frequency divider Q Q J K 1 Q Q J K 1 Q Q J K 1 Q Q J K 1 LSBMSBABCD E – clock A B C D f/2 f/4 f/8 f/16 f