0. Princess Sumaya University
Digital Logic Design
SEQUENTIAL LOGIC
CIRCUIT DESIGN
Dr. Bassam Kahhaleh

1. Princess Sumaya University
Digital Logic Design
Sequential Circuits
Asynchronous
Synchronous
Combinational
Circuit
Memory Elements
Inputs
Outputs
Combinational
Circuit
Flip-flops
Inputs
Outputs
Clock
Dr. Bassam Kahhaleh

2. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1
Initial Value
Dr. Bassam Kahhaleh

3. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1
Q = Q0 1
Dr. Bassam Kahhaleh

4. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1
Q = 0 1 1
Dr. Bassam Kahhaleh

5. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0
Q = 0 1 1 1
Q = 0
Dr. Bassam Kahhaleh

6. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0
Q = 0 1
Q = 1 1 1
Dr. Bassam Kahhaleh

7. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1
Q = 0
Q = 1 1
Q = 1 1
Dr. Bassam Kahhaleh

8. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1
Q = 0
Q = 1
Q = Q’ 1 1
Dr. Bassam Kahhaleh

9. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q0 Q Q’ 1
Q = Q0 1 1
Q = 0
Q = 1
Q = Q’
Q = Q’ 1
Dr. Bassam Kahhaleh

10. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q
0 0 Q0
0 1
1 0 1
1 1
Q=Q’=0
No change
Reset
Set
Invalid
S R Q
0 0
Q=Q’=1
0 1 1
1 0
1 1 Q0
Invalid
Set
Reset
No change
Dr. Bassam Kahhaleh

11. Princess Sumaya University
Digital Logic Design
Latches
SR Latch
S R Q
0 0 Q0
0 1
1 0 1
1 1
Q=Q’=0
No change
Reset
Set
Invalid
S’ R’ Q
0 0
Q=Q’=1
0 1 1
1 0
1 1 Q0
Invalid
Set
Reset
No change
Dr. Bassam Kahhaleh

12. Princess Sumaya University
Digital Logic Design
Controlled Latches
SR Latch with Control Input
C S R Q
0 x x Q0 1
Q=Q’
No change
Reset
Set
Invalid
Dr. Bassam Kahhaleh

13. Princess Sumaya University
Digital Logic Design
Controlled Latches
D Latch (D = Data)
Timing Diagram C D Q t
C D Q
0 x Q0
1 0
1 1 1
Output may change
No change
Reset
Set
Dr. Bassam Kahhaleh

14. Princess Sumaya University
Digital Logic Design
Controlled Latches
D Latch (D = Data)
Timing Diagram C D Q
C D Q
0 x Q0
1 0
1 1 1
Output may change
No change
Reset
Set
Dr. Bassam Kahhaleh

15. Princess Sumaya University
Digital Logic Design
Flip-Flops
Controlled latches are level-triggered
Flip-Flops are edge-triggered C
CLK
Positive Edge
CLK
Negative Edge
Dr. Bassam Kahhaleh

16. Princess Sumaya University
Digital Logic Design
Flip-Flops
Master-Slave D Flip-Flop
D Latch
(Master) D C Q
(Slave)
CLK
Master
Slave
CLK D
Looks like it is negative edge-triggered
QMaster
QSlave
Dr. Bassam Kahhaleh

17. Princess Sumaya University
Digital Logic Design
Flip-Flops
Edge-Triggered D Flip-Flop D Q
Positive Edge D Q
Negative Edge
Dr. Bassam Kahhaleh

18. Princess Sumaya University
Digital Logic Design
Flip-Flops
JK Flip-Flop J Q K
D = JQ’ + K’Q
Dr. Bassam Kahhaleh

19. Princess Sumaya University
Digital Logic Design
Flip-Flops
T Flip-Flop D Q T J Q K T T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q
Dr. Bassam Kahhaleh

20. Flip-Flop Characteristic Tables
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Tables D Q D
Q(t+1) 1
Reset
Set J K
Q(t+1)
Q(t) 1
Q’(t) J Q K
No change
Reset
Set
Toggle T Q T
Q(t+1)
Q(t) 1
Q’(t)
No change
Toggle
Dr. Bassam Kahhaleh

21. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations D Q D
Q(t+1) 1
Q(t+1) = D J K
Q(t+1)
Q(t) 1
Q’(t) J Q K
Q(t+1) = JQ’ + K’Q T Q T
Q(t+1)
Q(t) 1
Q’(t)
Q(t+1) = T  Q
Dr. Bassam Kahhaleh

22. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations
Analysis / Derivation J K
Q(t)
Q(t+1) 1
No change
Reset
Set
Toggle J Q K
Dr. Bassam Kahhaleh

23. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations
Analysis / Derivation J K
Q(t)
Q(t+1) 1
No change
Reset
Set
Toggle J Q K
Dr. Bassam Kahhaleh

24. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations
Analysis / Derivation J K
Q(t)
Q(t+1) 1
No change
Reset
Set
Toggle J Q K
Dr. Bassam Kahhaleh

25. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations
Analysis / Derivation J K
Q(t)
Q(t+1) 1
No change
Reset
Set
Toggle J Q K
Dr. Bassam Kahhaleh

26. Flip-Flop Characteristic Equations
Princess Sumaya University
Digital Logic Design
Flip-Flop Characteristic Equations
Analysis / Derivation J K
Q(t)
Q(t+1) 1 J Q K K 1 J Q
Q(t+1) = JQ’ + K’Q
Dr. Bassam Kahhaleh

27. Flip-Flops with Direct Inputs
Princess Sumaya University
Digital Logic Design
Flip-Flops with Direct Inputs
Asynchronous Reset D Q R
Reset R’ D
CLK
Q(t+1) x
Dr. Bassam Kahhaleh

28. Flip-Flops with Direct Inputs
Princess Sumaya University
Digital Logic Design
Flip-Flops with Direct Inputs
Asynchronous Reset D Q R
Reset R’ D
CLK
Q(t+1) x 1 ↑
Dr. Bassam Kahhaleh

29. Flip-Flops with Direct Inputs
Princess Sumaya University
Digital Logic Design
Flip-Flops with Direct Inputs
Asynchronous Preset and Clear D Q
CLR
Reset PR
Preset
PR’
CLR’ D
CLK
Q(t+1) 1 x
Dr. Bassam Kahhaleh

30. Flip-Flops with Direct Inputs
Princess Sumaya University
Digital Logic Design
Flip-Flops with Direct Inputs
Asynchronous Preset and Clear D Q
CLR
Reset PR
Preset
PR’
CLR’ D
CLK
Q(t+1) 1 x
Dr. Bassam Kahhaleh

31. Flip-Flops with Direct Inputs
Princess Sumaya University
Digital Logic Design
Flip-Flops with Direct Inputs
Asynchronous Preset and Clear D Q
CLR
Reset PR
Preset
PR’
CLR’ D
CLK
Q(t+1) 1 x ↑
Dr. Bassam Kahhaleh

32. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
The State
State = Values of all Flip-Flops
Example
A B = 0 0
Dr. Bassam Kahhaleh

33. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
State Equations
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
= A x + B x
B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
Dr. Bassam Kahhaleh

34. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
State Table (Transition Table)
Present State
Input
Next State
Output A B x y 1
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’ t
t+1 t
Dr. Bassam Kahhaleh

35. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
State Table (Transition Table)
Present State
Next State
Output
x = 0
x = 1 A B y 1 t
t+1 t
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Dr. Bassam Kahhaleh

36. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
State Diagram
Present State
Next State
Output
x = 0
x = 1 A B y 1 AB
input/output
0/0
1/0
0/1
0 0
1 0
0/1
1/0
0/1
1/0
0 1
1 1
1/0
Dr. Bassam Kahhaleh

37. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
D Flip-Flops
Example: D Q x
CLK y A
Present State
Input
Next State A x y 1 1
A(t+1) = DA = A  x  y
01,10 1
00,11
00,11
01,10
Dr. Bassam Kahhaleh

38. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
Present State
I/P
Next State
Flip-Flop Inputs A B x JA KA JB KB 1
JA = B KA = B x’
JB = x’ KB = A  x
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
Dr. Bassam Kahhaleh

39. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
JK Flip-Flops
Example:
Present State
I/P
Next State
Flip-Flop Inputs A B x JA KA JB KB 1 1 1
0 0
1 1
0 1
1 0 1 1
Dr. Bassam Kahhaleh

40. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
T Flip-Flops
Example:
Present State
I/P
Next State
F.F Inputs
O/P A B x TA TB y 1 1
TA = B x TB = x
y = A B
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB
= x  B
Dr. Bassam Kahhaleh

41. Analysis of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Analysis of Clocked Sequential Circuits
T Flip-Flops
Example:
Present State
I/P
Next State
F.F Inputs
O/P A B x TA TB y 1 1
0/0
0/0
0 0
1/0
0 1
1/1
1/0
1 1
1 0
0/1
0/0
1/0
Dr. Bassam Kahhaleh

42. Princess Sumaya University
Digital Logic Design
Mealy and Moore Models
The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15).
The outputs may change if the inputs change during the clock pulse period.
The outputs may have momentary false values unless the inputs are synchronized with the clocks.
The Moore model: the outputs are functions of the present state only (Fig. 5-20).
The outputs are synchronous with the clocks.
Dr. Bassam Kahhaleh

43. Princess Sumaya University
Digital Logic Design
Mealy and Moore Models
Fig Block diagram of Mealy and Moore state machine
Dr. Bassam Kahhaleh

44. Princess Sumaya University
Digital Logic Design
Mealy and Moore Models
Mealy
Moore
Present State
I/P
Next State
O/P A B x y 1
Present State
I/P
Next State
O/P A B x y 1
For the same state, the output changes with the input
For the same state, the output does not change with the input
Dr. Bassam Kahhaleh

45. Princess Sumaya University
Digital Logic Design
Moore State Diagram
State / Output 1
0 0 / 0
0 1 / 0 1 1
1 1 / 1
1 0 / 0 1
Dr. Bassam Kahhaleh

46. State Reduction and Assignment
Princess Sumaya University
Digital Logic Design
State Reduction and Assignment
State Reduction Reductions on the number of flip-flops and the number of gates.
A reduction in the number of states may result in a reduction in the number of flip-flops.
An example state diagram showing in Fig
Fig State diagram
Dr. Bassam Kahhaleh

47. Princess Sumaya University
Digital Logic Design
State Reduction
Only the input-output sequences are important.
Two circuits are equivalent
Have identical outputs for all input sequences;
The number of states is not important.
State: a b c d e f g
Input: 1
Output:
Fig State diagram
Dr. Bassam Kahhaleh

48. Princess Sumaya University
Digital Logic Design
Equivalent states
Two states are said to be equivalent
For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.
One of them can be removed.
Dr. Bassam Kahhaleh

49. Princess Sumaya University
Digital Logic Design
Reducing the state table
e = g (remove g);
d = f (remove f);
Dr. Bassam Kahhaleh

50. Princess Sumaya University
Digital Logic Design
The reduced finite state machine
State: a b c d e
Input: 1
Output:
Dr. Bassam Kahhaleh

51. Princess Sumaya University
Digital Logic Design
The unused states are treated as don't-care condition Þ fewer combinational gates.
Fig Reduced State diagram
Dr. Bassam Kahhaleh

52. Princess Sumaya University
Digital Logic Design
State Assignment
State Assignment
To minimize the cost of the combinational circuits.
Three possible binary state assignments. (m states need n-bits, where 2n > m)
Dr. Bassam Kahhaleh

53. Princess Sumaya University
Digital Logic Design
Any binary number assignment is satisfactory as long as each state is assigned a unique number.
Use binary assignment 1.
Dr. Bassam Kahhaleh

54. Princess Sumaya University
Digital Logic Design
Design Procedure
Design Procedure for sequential circuit
The word description of the circuit behavior to get a state diagram;
State reduction if necessary;
Assign binary values to the states;
Obtain the binary-coded state table;
Choose the type of flip-flops;
Derive the simplified flip-flop input equations and output equations;
Draw the logic diagram;
Dr. Bassam Kahhaleh

55. Design of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s 1
S0 / 0
S1 / 0
State
A B S0
0 0 S1
0 1 S2
1 0 S3
1 1 1
S3 / 1
S2 / 0 1 1
Dr. Bassam Kahhaleh

56. Design of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Output A B x y 1
S0 / 0
S1 / 0
S3 / 1
S2 / 0 1
Dr. Bassam Kahhaleh

57. Design of Clocked Sequential Circuits
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Output A B x y 1
Synthesis using D Flip-Flops
A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)
Dr. Bassam Kahhaleh

58. Design of Clocked Sequential Circuits with D F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops B 1 A x
DA (A, B, x) = ∑ (3, 5, 7)
= A x + B x
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
= A B B 1 A x B A 1 x
Dr. Bassam Kahhaleh

59. Design of Clocked Sequential Circuits with D F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
DA = A x + B x
DB = A x + B’ x
y = A B
Dr. Bassam Kahhaleh

60. Flip-Flop Excitation Tables
Princess Sumaya University
Digital Logic Design
Flip-Flop Excitation Tables
Present State
Next State
F.F.
Input
Q(t)
Q(t+1) D 1
Present State
Next State
F.F.
Input
Q(t)
Q(t+1) J K 1
0 0 (No change)
0 1 (Reset) 1
0 x
1 x
x 1
x 0
1 0 (Set)
1 1 (Toggle)
0 1 (Reset)
1 1 (Toggle)
0 0 (No change)
1 0 (Set)
Q(t)
Q(t+1) T 1 1
Dr. Bassam Kahhaleh

61. Design of Clocked Sequential Circuits with JK F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Flip-Flop
Inputs A B x JA KA JB KB 1
Synthesis using JK F.F.
JA (A, B, x) = ∑ (3)
dJA (A, B, x) = ∑ (4,5,6,7)
KA (A, B, x) = ∑ (4, 6)
dKA (A, B, x) = ∑ (0,1,2,3)
JB (A, B, x) = ∑ (1, 5)
dJB (A, B, x) = ∑ (2,3,6,7)
KB (A, B, x) = ∑ (2, 3, 6)
dKB (A, B, x) = ∑ (0,1,4,5)
0 x
1 x
x 1
x 0
0 x
1 x
x 1
x 0
Dr. Bassam Kahhaleh

62. Design of Clocked Sequential Circuits with JK F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using JK Flip-Flops
JA = B x KA = x’
JB = x KB = A’ + x’ B 1 A x B x A 1 B 1 x A B x 1 A
Dr. Bassam Kahhaleh

63. Design of Clocked Sequential Circuits with T F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
F.F. A B x
TA TB 1
Synthesis using T Flip-Flops 1 1
TA (A, B, x) = ∑ (3, 4, 6)
TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
Dr. Bassam Kahhaleh

64. Design of Clocked Sequential Circuits with T F.F.
Princess Sumaya University
Digital Logic Design
Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using T Flip-Flops
TA = A x’ + A’ B x
TB = A’ B + B  x B 1 A x B 1 A x
Dr. Bassam Kahhaleh