1. System Integration Module MTT48 5 - 1 Motoola SYSTEM INTEGRATION MODULE (SIM)

2. System Integration Module MTT48 5 - 2 Motoola Module Objectives Understand Reset handling performed by SIM Understand Interrupt handling performed by SIM Configure control registers for your system Module exercise: As part of reset servicing, determine which reset occurred and call an appropriate reset recovery routine.

3. System Integration Module MTT48 5 - 3 Motoola 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET System Integration Module Derives Bus clocks from CGM Bus clock generation and control for CPU and peripherals –Stop/wait/reset/break entry and recovery –Internal clock control Master reset control, including power-on reset (POR) and COP timeout Interrupt control: –Acknowledge timing –Arbitration control timing –Vector address generation CPU enable/disable timing Modular architecture expandable to 128 interrupt sources

4. System Integration Module MTT48 5 - 4 Motoola SIM Block Diagram CLOCK CONTROL CLOCK GENERATORS POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS MASTER RESET CONTROL RESET PIN LOGIC LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE RESET STOP/WAIT CONTROL SIM COUNTER COP CLOCK CGMXCLK (FROM CGM)  2

5. System Integration Module MTT48 5 - 5 Motoola System Integration Module - Bus Clocks - Takes output of Clock Generation Module Distributes clocks to submodules Controls system clocks in low power modes WAIT –Stops clock to CPU only STOP –Stops all bus clocks –Asserts SIMOSCEN Shuts down CGM oscillator circuit

6. System Integration Module MTT48 5 - 6 Motoola Reset Control MCU Reset Sources: Power-on Reset Module (POR) External Reset Pin (RST) Illegal Opcode Reset Illegal Address Reset –Caused by an opcode fetch from an illegal address Low-Voltage Inhibit Module (LVI) Computer Operating Properly Module (COP) WRITE: READ:PORPINCOPILOPILAD0LVI0 RESET:10000000 Reset Source Bit cleared by Reading SRSR or Power On Reset SRSR SIM Reset Status Register The SRSR records the cause of the last reset sequence. (One and only one bit will be set!)

7. System Integration Module MTT48 5 - 7 Motoola Voltage on V DD changes from logic zero to logic one Internal reset signal is asserted –Issues –All internal clocks to CPU and Modules are held inactive for 4096 CGMXCLK clock cycles –Allows for stabilization of oscillator –RST pin is driven low during stabilization of oscillator Power On Reset(POR) bit in SIM reset status register is set and all other bits in register are cleared. Power On Reset PORRST OSC1 CGMXCLK CGMOUT RST IAB 4096 CYCLES 32 CYCLES 32 CYCLES $FFFE$FFFF

8. System Integration Module MTT48 5 - 8 Motoola Power-On Reset Flow POR Pulse Vdd Oscillator begins operating Internal clocks held Low for 4096 CGMXCLK clock cycles RESET pin is driven low Reset pin is released.

9. System Integration Module MTT48 5 - 9 Motoola Internal reset signal can be generated by pulling RST* pin low PIN bit of the SIM reset Status Register (SRSR) is set if: –RST* held low for a minimum of 67 CGMXCLK cycles –PIN Bit Set Timing: POR/LVI Resets4163 = (4096 +64 + 3) Cycles All Other Resets67 = (64+3) Cycles External Pin Reset RST IABPC VECT HVECT L CGMOUT

10. System Integration Module MTT48 5 - 10 Motoola Internal Resets Illegal Opcode Reset Occurs when CPU decodes instruction not in opcode map Illegal Address Reset Occurs when CPU tries to fetch an instruction from an address not in defined memory map Low Voltage Inhibit Reset LVI indicates V DD dropped below preset limit Reset remains for 4095 CGMXCLK clock cycles after V DD is restored –Allows clock to stabilize Computer Operating Properly Reset COP indicates it’s timer has expired –Timer must be periodically reset System protection, prevents runaway processors ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET

11. System Integration Module MTT48 5 - 11 Motoola Internal Reset Timing IRST RST PULLED LOW BY MCU IAB 32 CYCLES VECTOR HIGH CGMXCLK

12. System Integration Module MTT48 5 - 12 Motoola Internal Reset Flow Internal Reset Signal is issued RST is actively driven low for 16 bus cycles Internal reset signal is asserted for 16 * additional bus clocks RST pin is tested RST pin low indicates that an external reset has occurred RST pin high indicates that an internal reset occurred and the appropriate internal reset bit is set * This is longer for LVI Reset

13. System Integration Module MTT48 5 - 13 Motoola Interrupts 68HC08 can process up to 128 separate resets/interrupts On-chip peripheral modules generate maskable interrupts Recognized only if interrupt mask bit clear Indicated by an interrupt status flag, also All interrupts are prioritized SIM module Receives all interrupts Performs arbitration Passes highest priority interrupt on to CPU

14. System Integration Module MTT48 5 - 14 Motoola 68HC708XL36 Interrupt Sources and Priorities LocalGlobal FunctionMaskMaskPriorityVector Address Resets (6/1)NoNone1$FFFE - $FFFF SoftwareNoNone2$FFFC - $FFFD Interrupt IRQ1YesI-bit3$FFFA - $FFFB PLL InterruptYesI-bit4$FFF8 - $FFF9 DMA YesI-bit5$FFF6 - $FFF7 Interrupts (3/1) TimerYesI-bit6$FFEC - $FFF5 Interrupts (5/5) SPI Interrupts (2/2)YesI-bit7$FFE8 - $FFEB SCI YesI-bit8$FFE6 - $FFE7 InterruptsYesI-bit9$FFE4 - $FFE5 (8/3)YesI-bit10$FFE2 - $FFE3 IRQ2/KeyboardYesI-bit11$FFE0 - $FFE1

15. System Integration Module MTT48 5 - 15 Motoola SIM Exercise Write a code sequence that determines what the last reset was and then calls an appropriate subroutine that implements a reset recovery scheme. The details of the called routines is not important. Given: * Reset service/recovery caller ORG$FE01 SRSRMB1 JMPTBLFDBPONRCVY FDBPINRCVY FDBCOPRCVY FDBILOPRCVY FDBILADRCVY FDBLVIRCVY

16. System Integration Module MTT48 5 - 16 Motoola Additional Information - Low Power Modes - WAIT Mode Control SIM stops CPU system clock Peripheral clocks continue to run Clears I-bit in CCR Exit conditions –Non-masked external interrupt –Any non-masked internal interrupt Module must also be active –Any Reset

17. System Integration Module MTT48 5 - 17 Motoola Additional Information - Low Power Modes - STOP Mode Control SIM Counter is reset and system clocks are disabled SIM disables clock generator outputs (CGMOUT and CGMXCLK) –CPU and Peripherals are stopped Clears I-bit in CCR Exit conditions –Non-masked external interrupt –External Reset only Recovery time is selectable –normal delay 4096 CGMXCLK cycles or –If SSREC = 1 in MOR(masked option register) delay 32 CGMXCLK cycles *Ideal for applications using canned oscillators not requiring long start-up times

18. System Integration Module MTT48 5 - 18 Motoola Additional Information - Break Status and Control - RESET:0 1. Writing a logic zero clears SBSW WRITE: READ:SBSW SBSR RESERVED NOTE 1 SIM Break Status Register (SBSR SIM Break Stop/Wait (SBSW) status bit –Useful in applications requiring a return to a wait or stop mode after exiting from a break interrupt 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt

19. System Integration Module MTT48 5 - 19 Motoola Additional Information - Break Status and Control - RESET:0 WRITE: READ: SBFCR RESERVED BCFE SIM Break Flag Control Register (SBFCR) *Enables software to clear status bits by accessing status registers while the MCU is in a Break state SIM Break Clear Flag Enable bit –To clear status bits during the break state, the BCFE bit must be set 1 = Status bits clearable during break 0 = Status bits not clearable during break

20. System Integration Module MTT48 5 - 20 Motoola Additional Information - Stabilization Delay - Mask Option Register (MOR) Short Stop Recovery –Selects either a long or short clock stabilization delay is to be used when exiting STOP 1 = Short stabilization delay (32 CGMXCLK clocks) For CAN Oscillator - off Board 0 = Long stabilization delay (4096 CGMXCLK clocks) On-board Oscillator RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD

21. System Integration Module MTT48 5 - 21 Motoola Register Summary RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD WRITE: READ:PORPINCOPILOPILAD0LVI0 RESET:10000000 Reset Source Bit cleared by Reading SRSR or Power On Reset SRSR

22. System Integration Module MTT48 5 - 22 Motoola SIM Exercise Solution * Reset service/recovery caller ORG$FE01 SRSRMB1 ResetLDHX#JMPTBL;Load base address of Jump table LDASRS;Read Reset Status Register CMP#$80;LVI Reset? BEQDONE;If so branch AIX#2;Offset = 2 CMP#$40;External Reset? BEQDONE;If so branch AIX#2;Offset = 4 CMP#$20;COP Reset? BEQDONE;If so branch AIX#2;Offset = 6 CMP#$10;ILOP Reset? BEQDONE;If so branch AIX#2;Must be ILAD Reset, Offset = 8 DONE JSR,X JMPTBLFDBLVIRCVY FDBPINRCVY FDBCOPRCVY FDBILOPRCVY FDBILADRCVY