1. Overview of Implementation Issues for Multitier Networks on DSPs Joseph R. Cavallaro Electrical & Computer Engineering Dept. Rice University August 17, 1999

2. Outline u Overview of Multitier Networks u DSP Rapid Prototyping Tools u Channel Estimation and Multistage Detection u DSP implementation and Real-time Issues u ASIC Implementation of Algorithm Modules u Conclusions and Future Directions

3. Multitier Overlay Networks Home Area Wireless LAN High Speed Office Wireless LAN Outdoor CDMA Cellular Network

4. Time Scales in Multitier Networks u Multiple Radio Interfaces u Reconfigurability and Commonality of Modules u Multitier Network Interface Card

5. mNIC Server Mobile Platform Network Protocols Proxy File System Transcoders Application Proxy Awareness mNIC N I C BS I N T E R N E T File System Network Protocols Proxy File System Transcoders

6. Current Group u Suman Das - Universal Baseline Software System u Vishwas Sundaramurthy - System Design Issues u Sridhar Rajagopal - Channel Estimation Algorithms u Oscar Pan – Real Time Workshop Implementation u Recent Graduates: – Chaitali Sengupta - ML Synchronization – Gang Xu - Differencing Multistage Detector

7. W-CDMA Simulation Testbed Overview u Development of an integrated software testbed u Unified framework to evaluate new algorithms for coding, synchronization, detection, etc. u Construction of a faster, efficient, and possibly hardware accelerated simulation testbed u TI TMS320C6201- TMS320C6701 based system – Base Station u TI TMS320C54 and FPGA / ASIC - Mobile

8. Software Rapid Prototyping Methodology DSP hardware DSP CODE HOST DSP CODE GENERATION TOOLS C - CODE WRAPPER (C - Code or Simulink) C mex - CODE MATLAB COMPILER MATLAB CODE u Communication and Signal Processing Algorithms in MATLAB and “C” u Faster Execution of “C” Code u Acceleration on DSP Boards u Multiple DSP Boards C - CODE

9. Simulink u Simulink – Good system for algorithm evaluation in communication systems and signal processing – Ties in well with MATLAB environment and functions – More intuitive than (C/Matlab) code based evaluation u Used in software version of wireless testbed

10. RTW u Real-Time Workshop – Generates ANSI C-code for Simulink block diagrams – Tool for DSP rapid prototyping – Quick but inefficient/non-optimized C-code u RTW support for C67x generation boards – Hardware (DSP)-in-the-loop simulations

11. Wireless Channel User_Data Show Stats Update Parameters Decorrelating Detector Multiuser Detector Error Counter Chip MF Max. Likelihood Channel Est. Channel Estimation CDMA Wireless System Testbed Simulink Version Parameters Multiuser Detection Channel Estimation AWGN Channel User Data Error Rate Calculation Statistics Chip matched filter

12. Hardware Platform Issues u Current System – TI TMS320C6201 and TMS32C6701 EVM boards u Multiple DSP Processor Configuration Issues and Task Decomposition. u Planned Upgrade to BlueWave, Spectrum

13. DSPs in Simulink based Wireless testbed u Use of C67 based boards for simulations – Useful for study of individual algorithms on C67 generation processors u Multiprocessing issues – Need block diagram partitioning and code generation support from Simulink/RTW – Need cleaner external communication mechanisms in the C67x DSP – Need support for controlling multiple DSPs

14. Architectural Issues u Memory – More internal memory for large temporary matrices u Prefetch Buffers – Matrices stored as arrays in memory. u ASIC /FPGA glue support – To explore HW acceleration of critical parts of the code u Specialized instructions : Square roots, reciprocals, rotations ?

15. Compiler Support u Compilers for VLIW – Scheduling & Tracking units difficult in manual assembly – Challenge to generate code to keep all units busy. – Small Operating System Support u Architectural improvements require coordinated advances in compiler support.

16. W-CDMA Software Testbed Experiments u Third generation wireless communication systems u Multimedia capabilities u Multirate services u Quality of service u Higher Data Rates: 2 Mbps, 384 Kbps, 144 Kbps.

17. The Wireless Channel : Multiuser, Multipath Direct Path Reflected Paths Faces Attenuation, Delays and Doppler Effects : Unknown Channel Parameters Antenna Noise + MAI Desired User

18. W-CDMA Base-Station Receiver Channel Estimator Multiuser Detector Demux Decoder Data Pilot Estimated Amplitudes & Delays Demodulator Antenna

19. CDMA Uplink System Channel Encoder Channel Encoder Channel Encoder Spreading AWGN Matched Filter Matched Filter Channel Estimator Matched Filter Multi- User Detector Channel Decoder + User 1 d 1 User 2 d 2 User K d K R(t) User 1 d 1 ' User 2 d 2 ' User K d K ' y1y1 y2y2 yKyK Demux

20. Maximum Likelihood - Channel Estimation u Send a time-multiplexed Preamble (Pilot). u Channel properties extracted from received signal. u Compare received signal with known pilot and estimate channel parameters. u Keep estimate for remaining data bits (static). u Repeat preamble every frame, if no tracking.

21. The Maximum Likelihood Algorithm u Compute the correlation matrices u Compute the channel estimate  Calculate the noise covariance matrix K.  Calculate the channel impulse response vector z. u Extract the ampitudes and delays from the channel impulse response vector using least squares fit.

22. The ML Algorithm Complexity u Complex-Real Dot Product. u Complex-Real Matrix Product. u Complex -Real Product. u Real Square roots. – Solving quadratic equation for least squares fit. u Critical code : Matrix-vector multiplications / Dot Product Assuming Unity Noise Covariance Offline

23. Differencing Multistage - Multiuser Detection u Based on the principle of Parallel Interference Cancellation (PIC) u Cross-correlation information used to remove interference of other users from desired user u Repeated iterations for convergence u Differencing techniques applied for improving the performance of the algorithm

24. The Differencing Multistage Detector u Split the crosscorrelation matrix into lower, upper and the diagonal matrix. u Calculate the channel impulse response iteratively using  x is called the differencing vector.

25. Multistage Detector Complexity u Matrix Multiplication: – Computed only once for one frame u Dot Product: – Computed iteratively u Critical code: Dot Product

26. TI Tools Used u Evaluation Modules (EVM) for C6201 and C6701 fixed and floating point DSPs – 64 KB each internal program & data memory – 256 KB SBSRAM, 8 MB SDRAM (external) u C Compiler ver 3.0 from Code Generation Tools u Code Composer ver 4.02 for profiling the code

27. DSP Implementation: Channel Estimation u Floating point implementation found more feasible due to matrix inversions and square-roots. u Code optimized for the DSP u Use of Specialized approximate instructions – Approximate reciprocal square roots – Approximate reciprocals u Use of Assembly Code for critical part. – TI's C67 floating point benchmarks for Matrix- Vector Multiplication & Dot Product u Data Memory requirements for Channel Estimation

28. Use of Approximate Instructions L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB 051015 0 20 40 60 80 100 120 140 Number of users --> Execution time(in milliseconds) --> Use of specialized instructions and assembly code on C6701 DSP C6701: Original C6701: with Intrinsics C6701: with Assembly 10% improvement 100% improvement

29. Optimization Effects for Channel Estimation 123 0 10 20 30 40 50 60 70 80 90 100 Effect of optimizations for Channel Estimation on C6701--> Execution time(normalized) --> Base (-o3 -pm) Approx. (-o3 -pm with intrinsics) Assembly opt. (-o3 -pm with asm) 2.34X improvement 1.08X improvement

30. Data Memory Requirements Data to be placed in External memory 130 6

31. DSP Implementation: Multistage Detection u 16-bit Fixed Point C Code u Code optimized for the DSP u Use of Assembly Code for critical part – TI's C62 fixed point assembly benchmarks for Dot Product u Data memory requirements for Multistage Detection

32. Optimization Effects for Multistage Detector 123 0 10 20 30 40 50 60 70 80 90 100 Effect of optimizations for Multistage Detection on C6201 --> Execution time(normalized) --> Global opt. (-o3 -pm -mu) Software Pipelining (-o3 -pm) Assembly opt. (-o3 -pm with asm) 5.22X improvement 7.47X improvement

33. Data Memory Requirements Data can be placed completely in Internal memory

34. Flops Count 12345678 0 2 4 6 8 10 12 14 x 10 4 Total Number of Iterations Number of Flops Users:K=15 SNR=6dB Conventional Method Differencing Method conventional differencing 2X speedup for a three-stage detector

35. Real-Time Requirements Real-Time capability by C6201 DSP NUMBER OF USERS 891011121314 50 100 150 200 250 300 350 MAX BIT RATE PER USER (kb/s) SNR=10dB WindowSize=12 Conventional Method Differencing Method 12users 150kb/s

36. Trends in Recent DSPs u More internal memory and higher clock speeds – C6203 : 512 KB data, 384 KB program, 250 MHz – useful for uplink channel estimation algorithms. u Specialized Blocks in the DSP Core. – Viterbi decoding in C54. u Lower Voltage operation – 1.2 V in C5402, useful for saving power consumption in the mobile.

37. ASIC Implementation u Differencing Multistage Detector Block u MOSIS Tiny-Chip (40-pin DIP) – 8 synchronous users – 12-bit fixed point implementation – 6000 transistors – 1.2  m CMOS technology – 190kb/s for each user (@12.5MHz) – 3-stage cascade delay < 15  s

38. Chip (Single Stage) Architecture SHIFT ALUALU RECODER REG (L+L’)A Control Logic Internal signals External signals

39. ASIC Architecture Features

40. Chip Layout 12-bit ALU Soft Decisions Cross- Correlation Recoding logic 2.0 mm

41. 3-stage Cascade Mode Sin Hin Fin Load CLK Sout Hout Fout 1/2 Sin Hin Fin Load CLK Sout Hout Fout 1/2 Sin Hin Fin Load CLK Sout Hout Fout 1/2 Matche d Filter Output Detector Output Hand Shakin g Load R Clock Output Valid

42. Current Work – GPP vs. DSP Joint work with Prof. Sarita Adve, Praful Kaul, and Parthasarathy Ranganathan Performance of general-purpose systems Comparing GPP and DSP performance Complete 3G benchmark suite with all components Identification of key performance bottlenecks

43. Preliminary Results (1 of 4) u (4 algorithms: channel estimation, multi-stage detection, FIR filter, dot product) u Performance of general-purpose processors – Instruction-level parallelism features help (3.4X to 4.4X) – Media ISA extensions help (1.2X to 5.4X) n New extensions for packing/multiplication useful u Comparing GPP and DSP performance – GPPs outperform DSPs n UltraSPARC-II+VIS 2-4X better than TI TMS320C6701 n Caveat: compiler issues with DSP

44. Preliminary Results (2 of 4) u Important to study complete system including all components – Need for complete benchmark suite SOURCE CODING CHANNEL CODING SPREADING DECODER DETECTOR DEMODULATION CHANNEL ESTIMATION user’s bits TRANSMITTER RECEIVER (BASE STATION) (MOBILE USER) detected bits of all K users K USERS MODULATION

45. Preliminary Results (3 of 4) u Complete 3G benchmark suite with all components Source coding Channel coding Spreading Modulation/De-modulation Multi-stage detection Channel estimation Channel decoding Source decoding u Used either public-domain or in-house “C” code n Optimized with ISA extensions

46. Preliminary Results (4 of 4) u Choice of source coding standard makes big difference – G728 system: source coding/decoding dominant – GSM system: channel estimation/detection dominant

47. Conclusions u Implementation issues : Estimation & Detection Algorithms u Channel Estimation - Floating Point / External Memory u Multistage Detection - Fixed Point / Internal Memory u Specialized instructions : square root/reciprocals. u Additional support for complex arithmetic useful. u Recent trends in GPP / DSPs highly encouraging for next generation wireless communication applications.

48. Future Work u FPGA / ASIC Implementation via VHDL models and SPW u Program & DSP implementations for W-CDMA uplink and downlink – Blind Algorithms – Adaptive Algorithms u Architectural bottlenecks and compiler issues in DSPs to enhance suitability for next generation W-CDMA systems u Multiple DSPs – mixed DSP / FPGA for mNIC