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11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan Hall 03/03/2005.

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Presentation on theme: "11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan Hall 03/03/2005."— Presentation transcript:

1 11 Wireless Sensor Networks (WISeNET) CPU Group Second Presentation Almir Davis Yong Zhang Halligan Hall 03/03/2005

2 22 Agenda  Project Description  Sensor Card Diagram  Sensor & Transceiver  CPU Design  CPU Open Issues  Questions from the Preliminary Presentation  Current Questions

3 33 Project Description The project’s objective is to design a network of independent sensors that would be able to sense the chemical structure of air’s particles and communicate the findings to the base computing station.

4 44 WSN Block Diagram

5 55 Sensor Card

6 66 Biochemical Sensors: A device incorporating a biochemical sensing element either intimately connected to or integrated within a transducer.

7 77 Biochemical Sensors Principles:

8 88 Current Sensors’ Detection Techniques  Surface wave acoustic detection  Ion mobility spectroscopy  Mass spectroscopy  Gas chromatography  Smart dust

9 99 CPU Block Diagram

10 10 CPU Receive

11 11 CPU Transmit (part a)

12 12 CPU Transmit (part b)

13 13 WSN CPU Arbitration

14 14 Open Issues  Shared sensor data bus  Clock frequency  “Active”, “Sleep” duty cycles  Internal CPU registers programmable wirelessly  In-Band Hot reset  Preamble size  Piggy-backed multi-sensor packets

15 15 Questions from the Preliminary Presentation  Can you put the CPU to sleep as well as the transceiver? –Transceiver can be put to sleep. CPU cannot.  In transceiver design you might want to separate RX & TX paths with different antennas to avoid collision. –Good observation. We will have separate control/data paths for the RX and TX side (reflected in the CPU design)  For power efficiency: A lot has to do with MOSFET scaling, voltage level, logic style, I/O pins. Will you address these issues? –We address the issue by reducing the number of IO pins, reducing the internal CPU memory size, and reducing the gate count by reducing the number of features. We will also address the issue of MOSFET scaling by choosing the vendor with a power efficient chip technology.

16 16 Questions from the Preliminary Presentation  Ambitious project, well thought through out, but will the end-product work? –  Warning! If everyone communicates to the base station it may lead to congestion, dropped messages etc… Need to clarify this transfer of data early on. –Na Wang, PH.D. student and the member of Professor’s Chang project team is assigned to deal with network related issues including the congestion issues.  Automatic power optimization after behavioral HDL code. –Good point. We do it at the RTL level but would appreciate your help if we are doing something wrong.

17 17 Questions from the Preliminary Presentation  How are you going to test the CPU before you build the CPU? –We will present the portion of the test right now …

18 18 ?


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