1. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 1 Chap 3. P-N junction  P-N junction Formation  Step PN Junction  Fermi Level Alignment  Built-in E-field (cut-in voltage)  Linearly Graded PN Junction  I-V Characteristics  Breakdown

2. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 2 Basic Symbol and Structure of the pn Junction Diode

3. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 3 Charge Distribution across PN junction

4. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 4 Step Junction N D - N A Actual Linearly Graded Profile x NDND -N A Ideal step junction Cathode Anode Metal contact p-type Si, N A n-type Si, N D –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– ––

5. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 5 Step P-N junction—Band Diagram ECEC EVEV EFEF E Fi ECEC EVEV EFEF P-Semiconductor N-Semiconductor ECEC EVEV EFEF E Fi ECEC EVEV EFEF Band Diagram Fermi-level alignment ECEC EVEV EFEF E Fi ECEC EVEV EFEF

6. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 6 Step Junction  Recall Poisson’s Equation:  For 1-D, E = E x dE/dx =  /k s  o where  = q (p – n + N D – N A )  For a pn junction, electrons and holes will diffuse through the junction, which would result in net  in the space charge region.

7. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 7 P-N Junction CathodeAnode Metal contact p-type Si, N A n-type Si, N D –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– + –  –– –– –– –– –– –– –– –– –– –– –– –– –– –– –– } Depletion region Ionized dopants

8. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 8 Charge Distribution in PN Junction  Net  results in the depletion region (or space charge region)   = -qN A -x p  x  0 qN D 0  x  x p xnxn  x + – -x p Charge neutrality

9. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 9 Open-Circuit Condition of a pn Junction Diode Potential hill 0 Barrier voltage } p-type Sin-type Si Depletion region CathodeAnode Metal contact Charge distribution of barrier voltage across a pn Junction.

10. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 10 Width of Space Charge Region  Recall x n N D = x p N A,  W is dependent on the built-in voltage V bi.

11. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 11 Reverse-Biased PN Junction Diode pn 3 VLamp Open-circuit condition (high resistance) V bi  V bi + V A W  

12. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 12 Forward-Biased PN Junction Diode pn 3 V Hole flowElectron flow Lamp V bi  V bi - V A W  

13. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 13 Bias Effect on the PN Junction

14. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 14 Bias Effect on the PN Junction Band Diagrams  Fig. 5.12

15. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 15 Linearly Graded PN Junction  Assume the linearly graded profile is N D – N A = ax, a: grading const.

16. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 16 Continuity Equations  There will be a change in carrier concentrations within a given small regions of the semiconductor if an imbalance exists between the total currents into and out of the region.  Minority Carrier Diffusion Equation

17. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 17 Continuity Equations  If thermal R-G is considered, continuity equations would be modified   Minority carrier Diffusion equations become

18. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 18 Diffusion Length  The average distance minority carriers can diffuse into a sea of majority carriers before being annihilated.

19. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 19 Quasi-Fermi levels  Are energy levels used to specify the carrier concentrations inside a semiconductor under nonequilibrium conditions. ECEFEiEVECEFEiEV Under equilibrium ECFNEiEVECFNEiEV FPFP Under non-equilibrium

20. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 20 PN Diodes: I-V Characteristics

21. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 21 Forward and Reverse Electrical Characteristics of a Silicon Diode 12010080604020.4.8 1.2 1.6 + I - V+ V - I Breakdown voltage Leakage current Reverse bias curve Forward bias curve Junction voltage

22. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 22 Composite energy-band/circuit diagram of a reverse-biased pn diode

23. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 23 I-V Characteristics  From deviation:  So for p + /n diode,  For n + /p diode,  As a general rule, this suggests that the heavily doped side of an asymmetrical junction can be ignored in determining the electrical characteristics of the junction.

24. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 24 Derivation of I-V Characteristics } p-type Sin-type Si Depletion region Quasi-neutral p region E ~ 0 Quasi-neutral n region E ~ 0 E0E0

25. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 25 Derivation of I-V Characteristics  In quasi-neutral regions, E = 0, so consider diffusion and thermal R-G currents only.  In Depletion Region:

26. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 26 Boundary conditions and quasi fermi level inside a forward- biased diode

27. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 27 Carrier Concentration inside a pn diode under forward and reverse biasing.

28. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 28 Experimental I-V Characteristics

29. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 29 Reverse-Bias Breakdown  Large reverse current flows when the reverse voltage exceeds a certain value, V BR. The current must be limited to avoid excessive “heating”.  Practical V BR measurements typically quote the voltage where the reverse current exceeds 1  A.  Factors to affect V BR : –1. Bandgap of the semiconductor to fabricate the pn diode –2. doping on the lightly doped side of the pn junction, N B  Breakdown Mechanism: –Avalanche process –Zener process

30. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 30 Avalanching As V A << V BR, the reverse current is due to minority carriers randomly entering the depletion region and being accelerated by the E-field. The acceleration is not continuous but is interrupted by energy-losing collisions with the semiconductor lattice. Since the mean free path between the collisions is ~10 -6 cm, and a median depletion width is ~10 -4 cm, a carrier can undergo 10-1000 collisions in crossing the depletion region. The energy lost by the carrier per collision is small. The energy transferred to the lattice simply causes lattice vibration --- local heating.

31. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 31 Avalanching  As V A  V BR, the amount of energy transfer to the lattice per collision increases dramatically, and becomes sufficient to ionize a semiconductor atom. That is to causes an electron from the valence band to jump to conduction band.  “impact ionization”  The electrons created by impact ioization are immediately accelerated by the large E-field in the depletion region, and consequently, they make additional collisions and create even more energetic electrons.  “Avalanching” Impact ionization

32. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 32 Zener Process  The occurrence of “tunneling” in a reverse-biased diode.  Two major requirements for tunneling to occur and be significant: –There must be filled states on one side of the barrier and empty states on the other side of the barrier at the same energy. –The width of the potential energy barrier must be very thin (< 10 nm ). –That is the doping on the “lightly” doped Si is in excess of 10 17 cm -3. –Zener process is only important in diodes that are heavily doped on both sides.

33. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 33 R-G Current  When diode is reverse biased, the carrier concentrations in the depletion region are reduced below their equilibrium values, leading to the thermal generation of electrons and holes throughout the region.  The large E-field in the depletion region rapidly sweeps the generated carriers onto the quasi-neutral regions, thereby adding to the reverse current. Reverse-biased generation Forward-biased recombination

34. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 34 Hetero-Junction ECEC EVEV EFEF E Fi Semiconductor A ECEC EVEV EFEF E Fi Semiconductor B EVEV ECEC  E C < 20 meV bulk Si E g = 1.17 eV Strained Si 0.8 Ge 0.2 E g ~ 1.0 eV  E V ~ 0.15 eV  E C ~0.15 eV  E V ~ 0.05 eV Relaxed Si 0.7 Ge 0.3 E g ~ 1.08 eV Strained Si E g ~ 0.88 eV Type I Alignment Type II Alignment

35. MOS Device Physics and Designs Chap. 3 Instructor: Pei-Wen Li Dept. of E. E. NCU 35 Quantum Well Hole Confinement  E C ~ 0.02 eV relaxed Si 0.7 Ge 0.3 E g = 1.08 eV Strained Si 0.3 Ge 0.7 E g ~ 0.72 eV  E V ~ 0.48 eV Strained Si Eg = 0.88 eV  E C ~0.18 eV  E V ~0.34 eV Electron Confinement