1. ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Documentation Standards (contd.)

2. 2 Previous… Block diagram Schematics Diagram Gate symbols Signal names Active levels for signal names/pins

3. 3 Bubble-to-Bubble Logic Design Purpose : To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators. ERROR FAIL_L OVERFLOW_L ERROR FAIL_L OVERFLOW_L

4. 4 Bubble-to-Bubble Logic Design Rules - The SIGNAL NAME of the output signal of a logic device should match the active level of the device’s output pin. Active-low if the device symbol has an inversion bubble, active-high if not. - If the active level of an input signal is the same as that of the device’s input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is asserted. Most common case. - If the active level of an input signal is the opposite of that of the input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is negated. Should be avoided. ERROR READY ERROR READY_L REQUEST ENABLE_L REQUEST ENABLE HALT_L ERROR OVERFLOW ERROR FAIL_L OVERFLOW_L

5. 5 Examples (Wakerly pp352)

6. 6 Another example

7. 7 Drawing Layouts Inputs to the left/top, outputs to the right/bottom. Signals flow from left to right (or top to bottom). Signal paths should be connected. Broken signal paths should be flagged to indicate the source or destination and direction. Crossing lines/Connected lines (T-type connection) Multiple pages schematics: - Flat Structure. - Hierarchical Structure.

8. 8 Drawing Layout: Flat schematic structure 4,6 5

9. 9 Hierarchical schematic structure

10. 10 Some rules to avoid common errors Use exactly the same name for same signal. Use different names for different signals. (especially cross pages) Use appropriate active levels for signal names Use “T” convention for connected lines.

11. 11 Buses Buses should be named : DATA[0:7], CONTROL A bus name may use brackets and a colon to denote a range Buses are drawn with thicker lines than ordinary signals. Individual signals are put into or pulled out of the bus by connecting an ordinary signal line to the bus and writing the signal name. (A special connection dot is often used.) A signal extracted from a bus should be named Inter-page signal/Bus Flags :  Uni-direction  Bi-direction Example: Figure 6-16, pp359 (next slide) DATA[0-7] DATA5 DATA6

12. 12

13. 13 Complete schematic diagram IC types: a part number identifying the IC that performs a given logic function. Also defines the device’s logic family and speed. E.g.. 74HCT00, 74LS00 Reference designators: each instance of that IC type installed in the system must have a unique, arbitrary number, e.g., U1,U2… Pin numbers: used to locate individual logic signal numbers on its pins. Check datasheets.

14. 14 Example schematic

15. 15 Logic Diagram to Schematic Diagram Logic Diagram Schematic Diagram Use Bubble-to-Bubble Logic Add IC-Type-Logic Family. See next slide for examples. Add Pin numbers- Pin Diagram Add Reference designator- Unique, arbitrary unit numbers based on chips used. A_L B_L F A_L B_L F 74LS04 74LS00 12 34 1 2 3 4 5 6 10 9 8U1 U2

16. 16 Dual-inline packages (74 series) www.Digikey.com

17. 17 Pinouts for SSI ICs in standard dual- inline packages (pp. 329) Small elements in 74x03 indicate an open-drain or open-collector output

18. 18 Combinational SSI devices (Contd.) Small elements in 74x14 hysteresis

19. 19 Combinational SSI devices (Contd.) Small elements in 74x266 indicate an open-drain or open-collector output

20. 20 Next… Reading Wakerly 6.1 6.2 Circuit Timing