1. 1 Characterization and modeling of the supply network from an integrated circuit up to 12 GHz C. Labussière (1), G. Bouisse (1), J. W. Tao (2), E. Sicard (3), C. Lochot (1) (1) Freescale Semiconductors, Toulouse, France (2) N7, Toulouse, France (3) INSA Toulouse, France

2. 2 Summary Context Objectives This work Measurement approach Experiments Model validation Conclusion

3. 3 1.Context Equipment designers want to ensure EMC before fabrication Courtesy C. Marot Siemens Automotive Toulouse Main source : micro-controller

4. 4 1. Context 16-bit micro-controller radiation in TEM cell, various programs dBµV 1 MHz10 MHz100 MHz1 GHz

5. 5 1. Context New concerns from 1 to 10 GHz 0 20 40 60 80 100 10MHz100MHz 1GHz Parasitic Emission (dBµV) 10GHz 100 GHz HC12 16 bit PowerPC 32 bits New bands of interest Frequency

6. 6 1. Context Pressure on IC vendors to provide parasitic emission models up to 5 GHz Existing standards to modelize IC core, internal supply network, I/O interface and package Models mostly valid up to 1 GHz Ibis ICEM

7. 7 2. This work Strategy to validate emission models for micro-controllers Simulations Core Model Package Model Probe Model Test board Model Analog Time Domain Simulation Fourier Transform Compare dBµV vs. frequency Measurements Fourier Transform Time-domain measure Frequency measurements This work

8. 8 2. This work Characterize the Passive Distribution Network (PDN) of a 16-bit µc Freescale (S12X family, QFP 144 pins) Build a specific board for high-precision measurements Investigate the impedance behavior up to 12 GHz Build a model based on R,L,C elements Promote this approach as part of the eXtended-ICEM model initiative

9. 9 3. Measurement approach Vector Network Analyzer Supply1 supply2 S ground Dut Base on [s] parameter characterization (s11, s12) RLC values tuned to fit with measurements R equi /2 L equi /2 R equi /2 L equi /2 C equi ground Supply1 Supply2

10. 10 [s] parameters of the DUT alone can be found by de- embedding using Thru-Reflect-Line (TRL method) measurement plane (short-open –load calibration) measurement plane DUT plane to network analyzer port 1 to network analyzer port 2 a1a1 b1b1 a2a2 b2b2 a’ 1 b’ 1 a’ 2 b’ 2 DUT transition line Non-coaxial Measurements Issue 3. Measurement approach

11. 11 1.Measurement of 3 calibration features with known [S] matrix [S] lineA meas. plane DUT plane meas. plane DUT plane [S] DUT [S] lineB Thru Reflect Line 3. Measurement approach Method (1/3)

12. 12 1.Measurement of 3 calibration features with known [S] matrix 2.Characterization of the transition lines [S] matrices [S] lineA meas. plane DUT plane meas. plane DUT plane [S] DUT [S] lineB [S] lineA [S] lineB 3. Measurement approach Method (2/3)

13. 13 1.Measurement of 3 calibration features with known [S] matrix 2.Characterization of the transition lines [S] matrices 3.Determination of the DUT [S] matrix by automatic de-embedding [S] DUT [S] lineA meas. plane DUT plane meas. plane DUT plane [S] DUT [S] lineB [S] -1 lineA [S] -1 lineB 3. Measurement approach Method (3/3)

14. 14 Lines type 2 Lines type 1 S12X SMA connectors “Reflect” type 2 “Reflect” type 1 “Thru” type 2 “Thru” type 1 High-frequency “Delay” type 1 High-frequency “Delay” type 2 Test boards Access+DUTCalibration boards 4. Experiments

15. 15 SS2 VDD1 VDD2 VSS1 VSSPLL VDDPLL VDDR1 VDDR2 VSSR2 VDDR1 VSSX2 VDDX2 VDDX1 VSSX1 VSSA VDDA S12X 144LQFP 8 pairs of VDD/VSS power and ground pins Nearly 120 possible measurements Select the key measurements to build the passive distribution network model 4. Experiments Test specification (1/2)

16. 16 4. Experiments Test specification (2/2) Port 1Port 2 VDD1VSS1 VDDAVSSA VDDX2VSSX2 VDDR1VSSR1.. VDD1VDDR1.. VSS1VSSR1 Logic core decoupling IO supply Substrate coupling Analog supply Other IO supply

17. 17 4. Experiments Measurement (1/2) 0.05 Ω VSSX1 VSSX2 VDDX2VDDX1 0.05 Ω VSSR1 VSSR2 VDDR2VDDR1 0.1 Ω 0.55 Ω0.75 Ω VSS1 VSS2 VDD2VDD1 1 Ω 0.9 Ω 0.05 Ω VSSA VDDA 0.05 Ω 12 Ω VSSPLL VDDPLL 25.9 Ω 0.2 Ω 0.15 Ω

18. 18 4. Experiments Measurement (2/2) VSS1-VSS2 [s12] up to 12 GHz Substrate coupling (R DC =1.8 ohm) Low impedance 1.8 GHz High impedance 900 MHz 5 GHz Inductive

19. 19 5. Model Validation Manual fitting of magnitude and phase by iteration Simulation Measure Simulation Measure

20. 20 5. Model Validation Partial model of the passive supply network including the inductive path and resistive coupling

21. 21 5. Model Validation VSS1-VSS2 [s12] up to 12 GHz Possible susceptibility issues 5 GHz 1 GHz

22. 22 Complete S12X supply network construction from 2- port [s] models T d1 T d2 T s1 T s2 T c VDD1VDD2 VSS1VSS2 [S VDD1-VDD2 ]  [T VDD1-VDD2 ] = [T d1 ]*[T d2 ] [S VSS1-VSS2 ]  [T VSS1-VSS2 ] = [T s1 ]*[T s2 ] [S VDD1-VSS1 ]  [T VDD1-VSS1 ] = [T d1 ]*[T c ]*[T s1 ] [S VDD2-VSS2 ]  [T VDD2-VSS2 ] = [T d2 ]*[T c ]*[T s2 ] [S VDD1-VSS2 ]  [T VDD1-VSS2 ] = [T d1 ]*[T c ]*[T s2 ]  [T d1 ], [T d2 ], [T c ], [T s1 ], [T s2 ]  [S d1 ], [S d2 ], [S c ], [S s1 ], [S s2 ]  spice-compatible behavioral model 5. Model Validation

23. 23 A technique for integrate circuit supply network characterization has been presented A specific board is required to characterize the impedance up to 12 GHz The technique is adaptable to BGA packages An impedance model has been derived, valid up to 12 GHz Resonance effects (0.9, 5 GHz) may generate susceptibility issues Conclusion