1. Status of integrated preamplifiers for GERDA GERDA meeting – MPI Heidelberg, Feb 20-22, 2006 F. Zocca, A. Pullia, S.Riboldi, C. Cattadori

2. Proposed circuit structure (from J. Gal*) * J. Gal et al. “Realization of charge sensitive preamplifiers using current feedback operational amplifier”, Nucl. Instrum. And Meth., Vol. A366, pp. 145-147, 1995

3. Test chip 3.3 mm MOSFETs resistors MOSFETs PREAMP 2 pMOS + ext R F + int bias Vmax = 550mV (50 Ohm) PREAMP 1 pMOS + ext R F + ext bias Vmax = 550mV (50 Ohm) PREAMP 1 PREAMP 2 PREAMP 3 pMOS + reset pMOS + shaper PREAMP 3 PREAMP 4 pMOS + ext R F + ext bias Vmax = 2V (1 kOhm) HIGH VOLTAGE comp’s TEST struct CSP+OS simple CC=0pF CSP+OS simple CC=0.2pF CSP+OS simple CC=0.6pF CSP+OS simple CC=1pF CSP+OS simple CC=1.4pF CSP+OS cplx CC=0pF CSP+OS cplx CC=2pF CSP+OS cplx CC=0.4pF CSP+OS cplx CC=1.4pF CSP+OS cplx CC=1pF OPAMP CSP + OS simple CSP with new rail-to-rail output stage. Various comp cap’s CSP + OS cplx CSP with new rail-to-rail output stage. Various comp cap’s Tested preamp

4. Test chip with wire bondings in 68LCC package Setup for cryogenic test

5. The output stage must be able to drive a coax/twisted pair cable (or a 100 to 200  load) and must provide the largest negative voltage swing (hole signals) Output stage & dynamic range At T=300°K, with a negative power supply V EE = - 3V, the circuit can drive a 10m coaxial cable of 50  still providing a negative voltage swing of ~ 2.5V At T=77°K the negative swing reached is of ~ 2.4V C F = ~ 0.15 pF, C test = 1 pF C det = 15 pF Energy sensitivity (in Ge) at the preamp output = ~ 370 mV/MeV (~185 mV/MeV if 50  terminated) Input dynamic range = ~ 6.5 MeV

6. Rise time at T = 300 °K driving a 50  coaxial cable of different lengths ~ 13 ns with ~1m cable ~ 15 ns with ~10m cable

7. Rise time at T = 77 °K driving a ~2m coaxial cable (50  ) A fast rise time of ~ 8 ns to ~ 13 ns has been obtained but a little overshoot has still to be eliminated by a low- pass filter or by reducing the preamp bandwidth a little bit 7.8 ns with no BW limit 13 ns with BW limit (equivalent to Anti-Aliasing filter)

8. Decay time constant ~ 200  s both at room temperature and in liquid nitrogen T = 300 °K T = 77 °K ~200  s C F = ~ 0.15 pF R F = 1.2 G 

9. Shaping time T=300°K ENC (el. r.m.s.) T=77 °K ENC (el. r.m.s.) 0.5  s 178325 1  s 148252 2  s 126191 3  s 118166 6  s 110128 10  s 111112 Noise measurements C det = 15 pF At T =77 °K the substantial increase of the white series noise is mainly due to the decrease of the JFET tranconductance

10. T = 300 °KT = 77 °K Energy sensitivity (C F = 0.15pF) ~ 370 mV/MeV at preamp output ~ 185 mV/MeV after 50  termination Negative output voltage swing ~ 2.5 V~ 2.4 V Input dynamic range~ 6.7 MeV~ 6.5 MeV Rise time ~ 13 ns with 1m coaxial cable ~ 15 ns with 10m coaxial cable ~ 13 ns with 2m coaxial cable (with little overshoot) ~ 15 ns with 10m coaxial cable (with little overshoot) Loop gain~ 500> 500 Minimum ENC (el. r.m.s.) with C det = 15pF 110 el. at  = 6  s112 el. at  = 10  s Power required ~ 177 mW (V FET = +12V I D = 14mA V CC = +2.5V V EE = -3V) ~ 22 mW (V FET = +4V I D = 3mA V CC = +3V V EE = -3V) Tested preamp specs

11. Future developments Optimization of tested preamplifier Tests with different values of C det and with values of C F ranging from 0.2 to 1 pF Tests of more preamplifiers (with different values of compensation capacitance) Design and test of a miniaturized setup Tests with different cable types and lengths Activity schedule March-June 2006: tests/optimization of existing chip. Design/realization of miniaturized PCB. Design of improved new chip. June-September 2006: realization of new chip / tests of old chip (continued) September-December 2006: tests of new chip