1. C-H1 Lecture Adders Half adder

2. C-H2 Full Adder si is the modulo- 2 sum of ci, xi, yi.

3. C-H3 An n-bit Ripple Adder FA Xn-1 Yn-1 Sn-1 Cn-1 Cn FA X0 Y0 S0 C0 C1 ……… MSBLSB

4. Adder/subtractor - = add 2’s complement of the subtrahend y xor 0 = y; y xor 1 = ~y C-H4

5. Overflow v.s. Carry-out n-bit signed number: -2 n-1 to 2 n-1 -1 Detect overflow for signed number: Overflow = C n-1 ⊕ C n Overflow = X n-1 Y n-1 ~S n-1 (110) + ~X n-1 ~Y n-1 S n-1 (001) where X and Y represent the 2’s complement numbers, S = X+Y. (sign bits 0, 0 ≠ 1 ) C-H5 Carry-out: for unsigned number 0111 1111

6. Propagate and Generate ripple carry c i+1 = x i y i + (x i +y i )c i = g i + p i c i A ripple-carry adder: critical path = 2n + 1 C-H6 x 1 y 1 g 1 p 1 s 1 Stage 1 x 0 y 0 g 0 p 0 s 0 Stage 0 c 0 c 1 c 2

7. Problem: ripple carry adder is slow

8. Carry-lookahead adder Motivation: – If we didn't know the value of carry-in, what could we do? –When would we always generate a carry? g i is true. g i = a i b i –When would we propagate the carry? p i is true. p i = a i + b i ci+1 = (bi.ci)+(ai.ci) +(ai.bi) = (ai.bi) + (ai+ bi).ci c2 = g1 + p1. c1 c3 = g2 + p2. c2 c4 is computed once inputs (a0-a3, b0 to b3, and c0) are valid.

9. Propagate and Generate Carry-Lookahead c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 g 0 + p 1 p 0 c 0 3 gate delays C-H9 D1 D2 D3

10. Hierarchical CLA: Build a 16-bit adder using a block of 4-bit CLA. Instead of producing the a carry-out from the most significant bit of the block, each block produces the generate and propagate signal for the entire block. –For block 0, looking into c4, if all the 4 propagate functions are 1, then the carry-in c0 is propagated through the entire block, hence P0 = p3.p2.p1.p0, the rest in c4 represents the cases when this block produces a carry-out with generates, thus G0 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 So, c4 = G0 + P0.c0

11. Second Level Equation The same principle as in the first level is used in the second level. The result of the second level is computed as soon as its inputs are valid. c4 = G0 + (P0.c0) c8 = G1 + (P1.G0) + (P1.P0.c0) c12 = G2 + (P2.G1) + (P2.P1.G0) +(P2.P1.P0.c0) c16 = G3 + (P3.G2) +(P3.P2.G1) + (P3.P2.P1.G0) +(P3.P2.P1.P0.c0) In block 0

12. A Multiplier Array C-H12 and adder

13. Array of Adders for Unsigned Multiplication C-H13 4-bit example