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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 P37X Non-Pipelined Datapath - Spring 2006
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 ALU1: 0000 Names: ______________________________ CSE372 Lab 3, part a
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 ALU2: 0001
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 TRAP: 0010
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 RTT: 0011
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 JUMP: 0100
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 JUMPR: 0101
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 JSR: 0110
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 JSRR: 0111
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 BR: 1000
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 CONST: 1001
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 INC: 1010
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 LEA: 1011
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 LDR: 1100
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 STR: 1101
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 LD: 1110
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PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr 4 16 4 I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] 3 3 3 Out 16 BR Logic 4’b0100 {I[12],I[2:0]} 4 3 16 1 ST: 1111
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