Presentation is loading. Please wait.

Presentation is loading. Please wait.

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

Published byMagnus Blair Modified over 9 years ago

Similar presentations

Presentation on theme: "CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina."— Presentation transcript:

1 CSCE 211: Digital Logic Design Chin-Tser Huang huangct@cse.sc.edu University of South Carolina

2 Verilog Hardware Description Language

3 Hardware Description Language Implementing a given function with an efficient set of logic gates could be a labor intensive and error prone procedure For combinational systems, need to develop truth table or algebraic expression, and manually simplify For sequential systems, need to translate state tables into logical expressions In the ’90s, designers found that it is more productive to specify just logical functions using hardware description language (HDL) and let a CAD tool to produce optimized gates Two leading HDLs: Verilog and VHDL 11/26/20133

4 Hardware Description Language Digital logic is either: Combinational F(inputs) = output Sequential F(inputs,input history) = output Some arrangement of off-the-shelf components inputsoutput inputsoutputs memory clk FA 11/26/20134

5 Verilog Modules Basic unit of design hierarchy Two types of modules: Behavioral: describe what a module does Structural: describe how a module is built from simpler modules One module per file File name is.v 11/26/20135

6 Verilog Syntax Case sensitive Example: reset and Reset are not the same signal No names start with numbers Example: 2mux is an invalid name Whitespace ignored Comments: // single line comment /* multiline comment */ 11/26/20136

7 Precedence ~ NOT *, /, %mult, div, mod +, -add,sub >shift >>arithmetic shift, >=comparison ==, !=equal, not equal &, ~&AND, NAND ^, ~^XOR, XNOR |, ~|OR, NOR ?: ternary operator Highest Lowest

8 Numbers Number# BitsBaseDecimal Equivalent Stored 3’b1013binary5101 ‘b11unsizedbinary300…0011 8’b118binary300000011 8’b1010_10118binary17110101011 3’d63decimal6110 6’o426octal34100010 8’hAB8hexadecimal17110101011 42unsizeddecimal4200…0101010 Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal)

9 Always Statement Need a mechanism for creating: Complex combinational logic Sequential logic Non synthesizable behaviors, e.g. clocks that repeat forever always @ (sensitivity list) statement; Whenever the event in the sensitivity list occurs, the statement is executed For multiple statements, use begin/end 11/26/20139

10 Always Statement Always statements allow additional programming constructs not available with assign statement: if statement case statement wire out1; assign out1 = sel ? foo : bar; — or — reg out1; always @(*) begin if (sel) out1 = foo; else out1 = bar; end 11/26/201310

11 Blocking vs. Nonblocking Assignments <= is a “nonblocking assignment” Occurs simultaneously with others (takes effect at end) = is a “blocking assignment” Occurs in the order it appears in the file Uses sequential semantics, used to build serialized paths 11/26/201311

12 Rules for Signal Assignment Use always @(posedge clk) or @(negedge clk) and nonblocking assignments (<=) to model synchronous sequential logic always @ (posedge clk) q <= d; // nonblocking Use continuous assignments (assign …) to model simple combinational logic. assign y = a & b; Use always @ (*) and blocking assignments (=) to model more complicated combinational logic where the always statement is helpful. Do not make assignments to the same signal in more than one always statement or continuous assignment statement 11/26/201312

13 Default Assignments For combinational logic, make sure all output signals are assigned on every control path Can use default signals to ensure this: module default_assignment_test (input sel, foo, bar, output reg out1); always @(*) begin out1 = bar; if (sel==1) out1 = foo; end endmodule 11/26/201313

14 Behavioral Verilog Example module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule 11/26/201314

15 Behavioral Verilog Example module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule 11/26/201315

16 Structural Modeling - Hierarchy module and3(input a, b, c, output y); assign y = a & b & c; endmodule module inv(input a, output y); assign y = ~a; endmodule module nand3(input a, b, c, output y); wire n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverter endmodule formal arguments actual arguments 11/26/201316

17 Arguments definition: module and3(input a, b, c, output y); assign y = a & b & c; endmodule instantiation: and3 andgate(a, b, c, n1); alternative instantiation: and3 andgate(.y(n1),.b(b),.a(a),.c(c)) 11/26/201317

18 Behavioral Verilog Example: Full Adder module full_adder(output c_out, s, input a, b, c); wire a, b, c; reg s, c_out; always @ (*) begin s = a ^ b ^ c; c_out = (a & b) | (a & c) | (b & c); end endmodule 11/26/201318

19 Structural Verilog Example: Full Adder module full_adder(output c_out, s, input a, b, c); wire a, b, c; wire s, c_out; wire w1, w2, w3; xor x1 (w1, a, b); xor x2 (s, w1, c); nand n1 (w2, a, b); nand n2 (w3, w1, c); nand n3 (c_out, w3, w2); endmodule 11/26/201319

20 Structural Verilog Example: 4-bit Adder module adder_4_bit(output [3:0] sum, output c, input [3:0] a, b); wire c0, c1, c2; full_adder f1 (c0, sum[0], a[0], b[0], ‘b0); full_adder f2 (c1, sum[1], a[1], b[1], c0); full_adder f3 (c2, sum[2], a[2], b[2], c1); full_adder f4 (c, sum[3], a[3], b[3], c2); endmodule 11/26/201320

21 Structural Verilog Example: D flip flop module D_ff(output q, input ck, D, CLR); reg q; always @ (negedge ck or negedge CLR) begin if (!CLR) q <= 0; else q <= D; end endmodule 11/26/201321

22 Structural Verilog Example: 8-bit Shift Register using D flip flops module shift(output [7:0] Q, input x, ck, CLR); D_ff Stage 7 (Q[7], x, ck, CLR); D_ff Stage 6 (Q[6], Q[7], ck, CLR); D_ff Stage 5 (Q[5], Q[6], ck, CLR); D_ff Stage 4 (Q[4], Q[5], ck, CLR); D_ff Stage 3 (Q[3], Q[4], ck, CLR); D_ff Stage 2 (Q[2], Q[3], ck, CLR); D_ff Stage 1 (Q[1], Q[2], ck, CLR); D_ff Stage 0 (Q[0], Q[1], ck, CLR); endmodule 11/26/201322

23 Structural Verilog Example: Single-Module Shifter module shift(input x, ck, CLR, output reg [7:0] Q); always (@ negedge ck) begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= Q[4]; Q[4] <= Q[5]; Q[5] <= Q[6]; Q[6] <= Q[7]; Q[7] <= x; end endmodule 11/26/201323

Download ppt "CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina."

Similar presentations

VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.

VERILOG: Synthesis - Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Rules Avoid technology dependent.
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering.

Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering.
The Verilog Hardware Description Language

The Verilog Hardware Description Language
Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
Synchronous Sequential Logic

Synchronous Sequential Logic
EE 361 Fall 2003University of Hawaii1 Hardware Design Tips EE 361 University of Hawaii.

EE 361 Fall 2003University of Hawaii1 Hardware Design Tips EE 361 University of Hawaii.
Combinational Logic.

Combinational Logic.
ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling.

ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling.
Table 7.1 Verilog Operators.

Table 7.1 Verilog Operators.
Verilog Intro: Part 1.

Verilog Intro: Part 1.
Hardware Description Language (HDL)

Hardware Description Language (HDL)
Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer.

Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer.
SYEN 3330 Digital SystemsJung H. Kim Chapter 4-3 1 SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.
CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling
Give qualifications of instructors: DAP

Give qualifications of instructors: DAP
1 Brief Introduction to Verilog Weiping Shi. 2 What is Verilog? It is a hardware description language Originally designed to model and verify a design.

1 Brief Introduction to Verilog Weiping Shi. 2 What is Verilog? It is a hardware description language Originally designed to model and verify a design.
 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  „ Widely used in logic design  „ Describe hardware  „ Document logic functions.

 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  „ Widely used in logic design  „ Describe hardware  „ Document logic functions.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level

CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Copyright © 2007 Elsevier4- Chapter 4 :: Hardware Description Languages Digital Design and Computer Architecture David Money Harris and Sarah L. Harris.

Copyright © 2007 Elsevier4- Chapter 4 :: Hardware Description Languages Digital Design and Computer Architecture David Money Harris and Sarah L. Harris.
Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities.

Similar presentations

Ads by Google