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Boolean and Sequential Logic Last week – Basic Gates AND OR NOT NOR XOR NAND.

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Presentation on theme: "Boolean and Sequential Logic Last week – Basic Gates AND OR NOT NOR XOR NAND."— Presentation transcript:

1 Boolean and Sequential Logic Last week – Basic Gates AND OR NOT NOR XOR NAND

2 This week Boolean Algebra Combining gates Using truth tables Sequential logic

3 Boolean Algebra

4 Combining gates

5 Truth table for previous slide AB CD EF 00 11 11 01 10 01 10 01 01 11 00 00

6 Truth table to logic diagram ABCDEFG 0011000 0110101 1001011 1100000

7 Looking at the truth table on the previous slide Output G is only true when the inputs A is false and B is true, or A is true and B is false. The output for an AND gate is only true when both the inputs are true, so if we build a circuit that when the combinations of inputs A is false and B is true, or A is true and B is false we get an true output we have built a circuit to do this logic operation.

8 A is false and B is true So if we can find a way to make the output from AND be true for this combination – part of the answer. There is no problem with B this is true. A is false so we need to pass it through a device that we A is false the output is true – NOT gate.

9 We can do a similar operation for when A is true and B is true We also need a way of combining these two parts together so if either combination occurs we get an true (1) output. OR gate

10 Combining gates

11 So far we have looked at combinational logic, put these gates together with a certain set of inputs, you always get a known output. Now we are going to consider combination of logic gates where what the previous output is important. This is sequential logic.

12 This ability to ‘remember’ a previous state extends what can be done with logic gates. Basis of simple memory

13 R-S Flip-Flop/Latch

14 For a R-S flip-flop based around the NOR gate. RSQ(time+1unit of time) 000- stays same (e.g. if 1 to starts then stays as 1) 011-Q is set to 1 100-Q is reset 11X-indeterminate (do not do this !)

15 D-type

16 Data (D) only appears at the output Q on a clock pulse. So if D=1 on a clock pulse, R=0,S=1 and Q=1. So if D=0 on a clock pulse R=1,S=0 and Q=0. Otherwise Q stays the same.

17 Summary Combining gate Using truth tables – Producing them – Using them to get a Boolean expression and logic diagram

18 Summary  Introduced the concept that an output can be feedback as an input, so the result is dependent on the previous state of the outputs as well as the inputs.  Simple memory (especially D-Type)

19 Sources for further reading (Boolean) Burrel (2004) Chapter 3 - pages 49 –57 Tanenbaum (2005) page 138-145 Dick(2003) page 98-101

20 Background reading (Sequential) Chalk et al (2004) pages 31-38 Tanenbaum (2005) pages 159-164


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