1. EE 5340 Semiconductor Device Theory Lecture 27 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2. ©rlc L27-28Apr20112 Fully biased n-MOS capacitor 0 y L VGVG V sub =V B E Ox,x > 0 Acceptors Depl Reg e - e - e - e - e - e - n+ VSVS VDVD p-substrate Channel if V G > V T

3. ©rlc L27-28Apr20113 MOS energy bands at Si surface for n-channel Fig 8.10**

4. ©rlc L27-28Apr20114 Computing the D.R. W and Q at O.S.I. ExEx E max x

5. ©rlc L27-28Apr20115 Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (  m)

6. ©rlc L27-28Apr20116 Fully biased n- channel V T calc

7. ©rlc L27-28Apr20117 n-channel V T for V C = V B = 0 Fig 10.20*

8. ©rlc L27-28Apr20118 Fully biased p- channel V T calc

9. ©rlc L27-28Apr20119 p-channel V T for V C = V B = 0 Fig 10.21*

10. ©rlc L27-28Apr201110 n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

11. ©rlc L27-28Apr201111 Conductance of inverted channel Q’ n = - C’ Ox (V GC -V T ) n’ s = C’ Ox (V GC -V T )/q, (# inv elect/cm 2 ) The conductivity  n = (n’ s /t) q  n G =  n (Wt/L) = n’ s q  n (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’ s q  n W)

12. ©rlc L27-28Apr201112 Basic I-V relation for MOS channel

13. ©rlc L27-28Apr201113 I-V relation for n-MOS (ohmic reg) IDID V DS V DS,sat I D,sat ohmic non-physical saturated

14. ©rlc L27-28Apr201114 Universal drain characteristic 9I D1 IDID 4I D1 I D1 V GS =V T +1V V GS =V T +2V V GS =V T +3V V DS saturated, V DS >V GS -V T ohmic

15. ©rlc L27-28Apr201115 Characterizing the n-ch MOSFET VDVD IDID D S G B V GS VTVT

16. ©rlc L27-28Apr201116 Substrate bias effect on V T (body-effect)

17. ©rlc L27-28Apr201117 Body effect data Fig 9.9**

18. ©rlc L27-28Apr201118 Low field ohmic characteristics

19. ©rlc L27-28Apr201119 MOSFET circuit parameters

20. ©rlc L27-28Apr201120 MOSFET circuit parameters (cont)

21. ©rlc L27-28Apr201121 Fig 10.51* MOSFET equivalent circuit elements

22. ©rlc L27-28Apr201122 MOS small-signal equivalent circuit Fig 10.52*

23. ©rlc L27-28Apr201123 MOS channel- length modulation Fig 11.5*

24. ©rlc L27-28Apr201124 Analysis of channel length modulation

25. ©rlc L27-28Apr201125 Channel length mod- ulated drain char Fig 11.6*

26. ©rlc L27-28Apr201126 e - e - e - e - e - + + + + + + + + + + + + Implanted n-channel enhance-ment MOSFET (ohmic region) 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat n+ p-substrate Channel e- channel ele + implant ion

27. ©rlc L27-28Apr201127 Si & SiO 2 AlAl Si 3 N 4 Si Si Al & SiO 2 Si 3 N 4 RangeRange RPRP Ion implantation*

28. ©rlc L27-28Apr201128 “Dotted box” approx**

29. ©rlc L27-28Apr201129 Calculating x i and  V T

30. ©rlc L27-28Apr201130 If x i ~ x d,max

31. ©rlc L27-28Apr201131 Calculating V T

32. ©rlc L27-28Apr201132 Implanted V T Vt per Eq. 9.1.23 in M&K for a MOSFET with an 87-nm-thick gate oxide, Q ff /q = 10 11 cm -2, N’ = 3.5 X 10 11 cm -2, and N a = 2 X 10 15 cm -3. Both V S and V B = Figure 9.8 (p. 441)

33. ©rlc L27-28Apr201133 Mobilities**

34. ©rlc L27-28Apr201134 Substrate bias effect on V T (body-effect)

35. ©rlc L27-28Apr2011 Body effect data Fig 9.9** 35

36. ©rlc L27-28Apr201136 M&K Fig. 9.9 (Eq. 9.1.23)

37. ©rlc L27-28Apr201137 Subthreshold conduction Below O.S.I., when the total band-bending < 2|  p |, the weakly inverted channel conducts by diffusion like a BJT. Since V GS >V DS, and below OSI, then N a >n S >n D, and electr diffuse S --> D Electron concentration at Source Concentration gradient driving diffusion

38. ©rlc L27-28Apr201138 M&K Fig.9.10 (p.443) Band diagram along the channel region of an n-channel MOSFET under bias, indicating that the barrier qΦ B at the source depends on the gate voltage.

39. ©rlc L27-28Apr201139 M&K Fig. 9.11 (p.444) Measured subthreshold characteristics of an MOS transistor with a 1.2 μm channel length. The inverse slope of the straight-line portion of this semilogarithmic plot is called the drain-current subthreshold slope S (measured in mV/decade of drain current).

40. ©rlc L27-28Apr201140 Subthreshold current data Figure 11.4* Figure 10.1**

41. ©rlc L27-28Apr201141 Mobility variation due to E depl Figures 11.7,8,9*

42. ©rlc L27-28Apr201142 Velocity saturation effects Figure 11.10*

43. ©rlc L27-28Apr201143 References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986