1. 2/15/02CSE 141 - Data Hazzards Data Hazards in the Pipelined Implementation

2. CSE 141 - Data Hazzards2 Pipelined Implementation Datapath Instruction Fetch Instruction Decode/ Register Fetch Execute/ Address Calculation Memory AccessWrite Back Note: The IF stage may be labeled “IM” (instruction memory) Mem labeled “DM” (data memory); WB labeled “Reg”

3. CSE 141 - Data Hazzards3 Data Hazards When a result is needed in the pipeline before it is available, a “data hazard” occurs. IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) R2 Available R2 Needed Time: 1 2 3 4 5 6 7 8 No hazard here Hazards! Value in register hasn’t been updated

4. CSE 141 - Data Hazzards4 Dealing With Data Hazards Transparent register file eliminates one hazard. Use latches rather than flip-flops in Reg file First half-cycle of cycle 5: register 2 loaded Second half-cycle: new value is read into pipeline state IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 and $12, $6, $5 or $13, $6, $8 add $14, $2, $2 R2 Available

5. CSE 141 - Data Hazzards5 Three ways to handle remaining Data Hazards In Software –insert independent instructions (or no-ops) In Hardware –insert bubbles (i.e. stall the pipeline) –data forwarding

6. CSE 141 - Data Hazzards6 Dealing with Data Hazards in Software IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 nop add $12, $2, $5 nop Insert enough no-ops (or other instructions that don’t use register 2) so that data hazard doesn’t occur,

7. CSE 141 - Data Hazzards7 Where are No-ops needed? sub $2, $1,$3 and $4, $2,$5 or $8, $2,$6 add $9, $4,$2 slt $1, $6,$7

8. CSE 141 - Data Hazzards8 Handling Data Hazards in Hardware Stall the pipeline sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 IMReg DMReg IMReg DM IMReg DMReg IMReg DMReg CC1CC2CC3CC4CC5CC6CC7CC8 Bubble

9. CSE 141 - Data Hazzards9 Pipeline Stalls To insure proper pipeline execution in light of register dependences, we must: –Detect the hazard –Stall the pipeline prevent the IF and ID stages from making progress –the ID stage because we can’t go on until the dependent instruction completes correctly –the IF stage because we do not want to lose any instructions. insert“no-ops” into later stages

10. CSE 141 - Data Hazzards10 The Pipeline What comparisons tell us when to stall?

11. CSE 141 - Data Hazzards11 Stalling the Pipeline Prevent the IF and ID stages from proceeding –don’t write the PC (PCWrite = 0) –don’t rewrite IF/ID register (IF/IDWrite = 0) Insert “nops” –set all control signals propagating to EX/MEM/WB to zero

12. CSE 141 - Data Hazzards12 The Pipeline

13. CSE 141 - Data Hazzards13 Reducing Data Hazards Through Forwarding Registers ID/EX ALU EX/MEMMEM/WB Data Memory 0101 IMReg ALU DMRegIMReg ALU DMReg add $2, $3, $4 or $5, $3, $2 We could avoid stalling if we could get the ALU output from “add” to ALU input for the “or”

14. CSE 141 - Data Hazzards14 Reducing Data Hazards Through Forwarding EX Hazard: if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 (similar for the MEM stage)

15. CSE 141 - Data Hazzards15 Data Forwarding Forwarding (just shown) handles two types of data hazards –EX hazard –MEM hazard We’ve already handled the third type (WB) hazard by using a transparent reg file –if the register file is asked to read and write the same register in the same cycle, the reg file allows the write data to be forwarded to the output.

16. CSE 141 - Data Hazzards16 Eliminating Data Hazards via Forwarding IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 and $6, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

17. CSE 141 - Data Hazzards17 Does Forwarding eliminate all hazards?? IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 lw $2, 10($1) and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

18. CSE 141 - Data Hazzards18 NO! You may need to stall after loads IMReg ALU DMReg IMReg ALU DM IMReg ALU DMReg IMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 lw $2, 10($1) and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) IMReg ALU Bubble

19. CSE 141 - Data Hazzards19 Try this one... Show stalls and forwarding for this code add $3, $2, $1 lw $4, 100($3) and $6, $4, $3 sub $7, $6, $2

20. CSE 141 - Data Hazzards20 Data Hazard Key Points Pipelining provides high throughput, but does not handle data dependences easily. Data dependences cause data hazards. Data hazards can be solved by: –software (no-ops) –hardware stalling –hardware forwarding Our processor, and indeed all modern processors, use a combination of forwarding and stalling.