1. Slide 1 / 14 PSFEB Status Report LHCb Team @ Clermont Production Test preview of the PreShower Front-End Boards February the 1 rst, 2007

2. Slide 2 / 14 PSFEB Status Report LHCb Team @ Clermont Production Test organisation Interface automated tests : Manual interventions : DAQ test with Analogic Wave Generator (sine signal) Long term tests: Provide dedicated data- sheets for valid boards I2C communication Phasers Connectivity Algorithm Characteristics measure - Measure the offsets - Bit Flip Rate failure for TrigPGA - AOB ? Pedestal fluctuations …

3. Slide 3 / 14 PSFEB Status Report LHCb Team @ Clermont Production Test Interface (1/3) 2. Fill the header part 1. Initialize the VME crate -‘Resman’ program (Resource Manager) - a simple test : flickering the memory board LEDs 3. Load a list of processes from an option file Compulsory steps for launching the test (enabling the GO button) - the board ID number - user name (to choose in a list) - PC DNS name - the crate used - CAT release (is automatically set) ‘Track test conditions’

4. Slide 4 / 14 PSFEB Status Report LHCb Team @ Clermont Production Test Interface (2/3) Possibility to change easily some test parameters from the interface (title, number of events, threshold) A board is rejected if for one process : number of errors > threshold A board is accepted if for all processes : number of errors <= threshold

5. Slide 5 / 14 PSFEB Status Report LHCb Team @ Clermont Production Test Interface (3/3)

6. Slide 6 / 14 PSFEB Status Report LHCb Team @ Clermont List of processes file Name of the CAT process Name of the CAT element which will be tested by the process Title of the process in the Production Test interface Number of events, threshold Delay (ms) applied just before the process running Name of the specific log file for the process Possibility to reset GLUE or SPECS Mezzanine before the process running

7. Slide 7 / 14 PSFEB Status Report LHCb Team @ Clermont Log outputs C: LHCb CAT CATLPC Production 001 Number of the board 001 directory Detailed log file for each process Global log file Explicit ASCII data files Collected in separate folders

8. Slide 8 / 14 PSFEB Status Report LHCb Team @ Clermont Log outputs : html browser C: LHCb CAT CATLPC Production 001 Number of the board 001 Parse the log files to.html Parsed global log file Provide an html browser for log files TODO: index.html with boards status summary +link to logs & data sheets Index.html

9. Slide 9 / 14 PSFEB Status Report LHCb Team @ Clermont Log outputs : html browser Quick status Expanded status Popup link to detailed log

10. Slide 10 / 14 PSFEB Status Report LHCb Team @ Clermont Table of processes & timing (1/2) I2C communication I2C communication  8 FePGA registers8x1000  8 FePGA parameters8x100  TrigPGA registers1000  TrigPGA injection RAM3  SEQ1000  3 delay chips3x1000 4min30s Phaser 1 Phaser 1  SPD1  TOP neighbours1  ECAL1 1min Intraconnectivity FePGA - TrigPGA Intraconnectivity FePGA - TrigPGA PS & SPD, 4 Mapping2x4x5 2min

11. Slide 11 / 14 PSFEB Status Report LHCb Team @ Clermont Table of processes & timing (1/2) Connectivity with other boards Connectivity with other boards  Inputs : SPD, ECAL add & BCID, Top & Right neighbours  Outputs : multiplicity, TVB clusters, Bottom & Left neighbours 5 evts 30s FePGA algorithms FePGA algorithms TrigPGA algorithmsTrigPGA algorithms  Offsets + Trigger bits : 8x5  Gain + Trigger bits : 8x5  Alpha + Trigger bits : 8x5 4min Global tests with RAMs + 4 mapping4x5 + 2 inversion4x5 3min30 Total duration :16min “offset computation” & “bit flip rate determination” processes haven’t been implanted in this protocol yet.

12. Slide 12 / 14 PSFEB Status Report LHCb Team @ Clermont Results of the production test for boards 001 & 002 Board 001 (TrigPGA APA 450) Output Left PS neighbours : 4% error rate on bit #6 (after mapping) Details in ‘TestCONNECT_OUTPUT_neighbours.dat’ Bit Flip Rate threshold :18% Offsets :? Board 002 (TrigPGA APA 600) OK (?) Bit Flip Rate threshold :18% Offsets :? Interface automated tests : +known issues : phasers blocking Manual interventions : DAQ test with Analogic Wave Generator (sine signal) ? Long term tests: Pedestal fluctuations : ?

13. Slide 13 / 14 PSFEB Status Report LHCb Team @ Clermont Documentation An illustrated user guide A brief list of the processes A description of each process To be achieved

14. Slide 14 / 14 PSFEB Status Report LHCb Team @ Clermont SUMMARY Tasks to be done : Implant “offset computation” & “bit flip rate determination” processes into the production test interface  DONE AWG : GPIB issues update “pipeline registers test” processes for completing the current list test the next release of the TrigPGA and write a process for testing its new functionality  Messy I/Os web access for the board datasheets  ongoing … complete the documentation A first catalog of processes is available for testing the pre-series boards !

16. Current list of processes I 2 C Communication PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS PsFePGA_I2CPS_FE_PGAPsFEPGA_I2C.cppConfiguration registers: Takes into account the FEPGA release version. OK PsFePGA_I2C_PARPS_FE_PGAPsFEPGA_I2C_PAR.cppFE-PGA Configuration parametersOK PsFePhaser_I2CPhaser 0, 1, 2PsFePhaser_I2C.cppOK Test I2C Ps_SeqPGASeq_PGAPsFeSeq_I2C.cppOK PSTrigPGA_I2C_INJRAMPsTrig_PGAPsTrigPGA_I2C_INJRAM.cppOK PSTrigPGA_I2C_CONFIGPsTrig_PGAPsTrigPGA_I2C_CONFIG.cpp TRIG Configuration parameters OK Connectivity PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS Test_Connectivity FEPGA – TRIGA PS bits + 4 mapping type FEBPsTrigPGA_PROC_IntraConnectivity.cppTest FE-TRIG intra connectivity + mappings algorithms OK Test_Connectivirt FEPGA – TRIGA SPD bits + 4 mapping type PsTrigPGA_PROC_IntraConnectivity.cppOK INPUT : SPD + RIGHT NEIGHBOURS FEBPsTrigPGA_PROC_InputTest.cpp FEB I/Os Mem. BoardsOK INPUT : ECAL addressesOK INPUT : ECAL BCIDOK INPUT : TOPOK INPUT : RIGHT CORNEROK OUTPUT : multi, ECAL addresses, BCIDs OK OUTPUT : neighboursOK OUTPUT : VAL1 & VAL2OK

17. Current list of processes Phaser Test PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS Phaser 1 test : ECALFEBPsTrigPGA_PhaserTestMem. BoardsOK Phaser 1 test : SPDFEBPsTrigPGA_PhaserTestOK Phaser 1 test : TOP neighboursFEBPsTrigPGA_PhaserTestOK DAQ Algorithms PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS PsFePGA_PROC_OFFSETPS_FE_PGAPsFe_PGA_PROC_OFFSET.cppinjRAM, acqRAM + chan. BOK PsFePGA_PROC_GAINPS_FE_PGAPsFe_PGA_PROC_GAIN.cppOK PsFePGA_PROC_ALPHAPS_FE_PGAPsFe_PGA_PROC_ALPHA.cppOK Trigger Algorithms PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS Global ProcessFEBPsTrigPGA_PROC_GlobalProcess.cpp injRAM, acqRAM + chan. B OK Global Test with Memory BoardsFEBPsTrigPGA_PROC_GlobalProcessWithTB.cppMem. BoardsOK, to include Full DAQ Path PROCESS NAMEELEMENT TYPECATProc FILEINFO Specific devices STATUS Ps Offset CalculationFEBPsPedestals.cppPedestals measurementOK, to include DAQ through ACQRAM FEB PSFEB_ACQRAM.cppData acquired with CROCs SPYRAM AWGGPIB issue ? Ps_data acqusition DAQ PSAcquisition.cppData acquired with CROCs SPYRAM