1. EE3A1 Computer Hardware and Digital Design Worked Examples 3 Test and testability (1)

2. Worked Examples (a) Explain testability enhancement.[5] (b) Form Boolean difference of the output with respect to each of the inputs. [8] (c) Produce a set of test vectors that can test the inputs a,b,c for single s-a-0 and s-a-1 faults.[3]

3. Worked Examples (d) Signature analyser initialized to the all-zero state, and fed with 111011011 (MSB first ). i) What is the fault-free signature? ii) Show that if the fifth bit is in error, the final signature is different from the fault-free case. [4]

4. Solution: part (b)  Form Boolean difference of the output with respect to each of the inputs. (c) Circuit function is Likewise for b and c Boolean proposition: if a changes then f will also change This is true when setting a=1 and a=0 give rise to different value for f f0f1f0 XOR f1 000 011 101 110

5. Solution: Sensitivity to a (b) Circuit function is Using identity X  Y=X.Y+X.Y

6. Solution: Sensitivity to b (b) Circuit function is Using identity X  Y=X.Y+X.Y

7. Solution: Sensitivity to c (b) Circuit function is Using identity X  Y=X.Y+X.Y

8. Solution: part (b) What does this mean?

9. Meaning of Boolean Difference 000010 001010 010111 011100 100111 101111 110111 111100 Truth table for f K-Map for f

10. Meaning of Boolean Difference K-Map for f Where b is changing: is true if change in b causes change in f Where change in f results

11. Meaning of Boolean Difference Where b is changing: K-Map for f is true if a change in b causes a change in f Where change in f results

12. Questions  What is the value of  (i.e. under what condition will a change in A cause a change in C) (a) a+b (b) 1 (c) a (d) b (e) b

13. Solution: part (c) Test a, b and c for s-a-0, s-a-1

14. Solution: part (c) node a Test a s-a-0 Set a=1 Make f sensitive to a b=0 Test vector abc=100 or 101 Test a s-a-1 Set a=0 Make f sensitive to a b=0 Test vector abc=000 or 001

15. Solution: part (c) node b Test b s-a-0 Set b=1 Make f sensitive to b ac=11 or 00 Test vector abc=111 or 010 Test b s-a-1 Set b=0 Make f sensitive to b ac=11 or 00 Test vector abc=101 or 000

16. Solution: part (c) node c Test c s-a-0 Set c=1 Make f sensitive to c b=1 Test vector abc=011 or 111 Test c s-a-1 Set c=0 Make f sensitive to c b=1 Test vector abc=010 or 110

17. Solution: part (d)  Initialized to 0 and fed with 111011011 (MSB first ).  What is 4-input XOR?

18. XOR gates abcdout 00000 00011 00101 00110 01001 01010 01100 01111 10001 10010 10100 10111 11000 11011 11101 11110 a b c d a b c d Output is high when odd number of inputs is high

19. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 1 1 0 1 1 0 1 1 1000001

20. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 1 0 1 1 0 1 1 1010000

21. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 0 1 1 0 1 1 1001000

22. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 1 1 0 1 1 0000010

23. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 1 0 1 1 1000101

24. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 110001 0 1 1 1110001

25. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 110001 011000 1 1 0011000

26. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 110001 011000 101100 1 1001010

27. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 110001 011000 101100 100110 1000111

28. Solution: part (d)  Fed with 111011011 (MSB first ). InputTest 100000 110000 101000 000100 100010 110001 011000 101100 100110 10011 11010

29. Part (d): 5 th bit in error  Fed with 111011011 (MSB first ). InputTest 100000 1 1 0 1 1 0 1 1 100000

30. Part (d): 5 th bit in error  Fed with 111001011 (MSB first ). InputTest 100000 1 1 0 0 1 0 1 1 1000001

31. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 1 0 0 1 0 1 1 1010000

32. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 0 0 1 0 1 1 1001000

33. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 0 1 0 1 1 0000010

34. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 1 0 1 1 0000100

35. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 100001 0 1 1 1100000

36. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 100001 000000 1 1 0000000

37. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 100001 000000 1 1 1000001

38. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 100001 000000 1 110000 1010000

39. Solution: part (d)  Fed with 111001011 (MSB first ). InputTest 100000 110000 101000 000100 000010 100001 000000 1 110000 01000 00100  Signature is different  This fault is detected