1. 1/16/2016 1 CSEE, UQ Lecture 3 Hardware Description Methods, Review of Switching Algebra

2. 1/16/2016 2 CSEE, UQ x1=x0= (a) Two states of a switch S x (b) Symbol for a switch A binary switch

3. 1/16/2016 3 CSEE, UQ (a) Simple connection to a battery S x (b) Using a ground connection as the return path L BatteryLight x Power supply S L A light controlled by a switch

4. 1/16/2016 4 CSEE, UQ (a) The logical AND function (series connection) S x 1 L Power supply S x 2 S x 1 L Power supplyS x 2 (b) The logical OR function (parallel connection) Light Two basic functions

5. 1/16/2016 5 CSEE, UQ S x 1 L Power supplyS x 2 Light S x 3 A series parallel connection

6. 1/16/2016 6 CSEE, UQ S x L Power supply R An inverting circuit

7. 1/16/2016 7 CSEE, UQ Truth table for AND and OR

8. 1/16/2016 8 CSEE, UQ Three input AND and OR

9. 1/16/2016 9 CSEE, UQ x 1 x 2 x n x 1 x 2 x 1 x 2. x 1 x 2 … x n. (a) AND gates (b) OR gates x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 … x n +++ Basic gates x x (c) NOT gate x 1 x 2 x 1 x 2. x 1 x 2 x 1 x 2 + (d) NAND gate (e) NOR gate

10. 1/16/2016 10 CSEE, UQ x 1 x 2 1100 f 0001 1101 0011 0101 (a) Network that implements fx1x1 x1x1 x2x2 += x 1 x 2 fx 1 x 2,() 0 1 0 1 0 0 1 1 1 1 0 1 (b) Truth table for f A B Logic network

11. 1/16/2016 11 CSEE, UQ 1 0 1 0 1 0 1 0 1 0 x 1 x 2 A B f Time (c) Timing diagram 11000011 1101 0101 g x 1 x 2 (d) Network that implementsgx 1 x 2 += Logic network

12. 1/16/2016 12 CSEE, UQ Boolean algebra - axioms 0*0 = 0 1 + 1 = 1 1*1 = 1 0 +0 = 0 0* 1 = 1* 0 = 0 1 + 0 = 0 + 1 = 1 x*0 = 0 x + 1 = 1 x*1 = x x +0 = x x* x = x x + x = x x* x = 0 x+ x = 1 x = x x*y = x + y x + y = x*y x + x*y = x + y x*(x + y) = x*y DeMorgan laws

13. 1/16/2016 13 CSEE, UQ DeMorgan’s theorem

14. 1/16/2016 14 CSEE, UQ Figure 2.12 The Venn diagram representation Please see “portrait orientation” PowerPoint file for Chapter 2

15. 1/16/2016 15 CSEE, UQ Figure 2.13 Verification of the distributive property Please see “portrait orientation” PowerPoint file for Chapter 2

16. 1/16/2016 16 CSEE, UQ Please see “portrait orientation” PowerPoint file for Chapter 2 Figure 2.14 Verification example

17. 1/16/2016 17 CSEE, UQ A function to be synthesised

18. 1/16/2016 18 CSEE, UQ f (a) Canonical sum-of-products f (b) Minimal-cost realization x 2 x 1 x 1 x 2 Two implementations

19. 1/16/2016 19 CSEE, UQ Minterms and maxterms

20. 1/16/2016 20 CSEE, UQ A three variable function

21. 1/16/2016 21 CSEE, UQ (a) A minimal sum-of-products (b) A minimal product-of-sums f x 1 x 2 x 3 f x 2 x 1 x 3 Two implementations

22. 1/16/2016 22 CSEE, UQ Three way light controller A room with three doors. Light switch at each door. Light turned on/off at each door. 1 - turned on. 0 – turned off. Specification (for logic only):

23. 1/16/2016 23 CSEE, UQ f x 1 x 2 x 3 Sum of Products – SOP

24. 1/16/2016 24 CSEE, UQ f x 1 x 2 x 3 Products of Sums – POS

25. 1/16/2016 25 CSEE, UQ (a) Truth table f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit (d) More compact truth table 0000 0010 0101 0111 1000 1011 1100 1111 sx1x1 x2x2 f (s, x 1, x 2 ) 0 1 s x1x1 x2x2 f x 1 x 2 s Multiplexer

26. 1/16/2016 26 CSEE, UQ (a) Truth table (c) XOR Graphical symbol (b) One of XOR Circuits XOR, XNOR gates 000 011 101 110 x1x1 x2x2 XOR 1 0 0 1 XNOR f x 1 x 2 (d) XNOR Graphical symbol

27. 1/16/2016 27 CSEE, UQ Waveform Editor

28. 1/16/2016 28 CSEE, UQ Graphic Editor

29. 1/16/2016 29 CSEE, UQ Please see “portrait orientation” PowerPoint file for Chapter 2

30. 1/16/2016 30 CSEE, UQ f x 3 x 1 x 2 first touch of VHDL

31. 1/16/2016 31 CSEE, UQ A bit more of VHDL

32. 1/16/2016 32 CSEE, UQ f g x 3 x 1 x 2 x 4 Four-input function