1. ITRS 2000 Update Work In Progress - Do Not Publish! 1 ITRS/ Design TWG Update 2000 System on Chip, Design Productivity, Low Power, Deep Submicron Design requirements, Future role of Design TWG Proposal ITRS 2000 Update Contact: Werner Weber, +49 89 48470, werner.weber@infineon.com

2. ITRS 2000 Update Work In Progress - Do Not Publish! 2

3. 3 Scenario: major increase in memory content

4. ITRS 2000 Update Work In Progress - Do Not Publish! 4 Comments: I feel that we should remember the premises and the motivations for that exercise: "what should we do to increase the design productivity, and keep the size of the design team constant (10 man-year)?" Is this exercise useful, I don't know. The solution found by the STRJ consists in putting less logic (more memories) and do more reuse. Anyway 10% of logic in year 2011 gives a significantly high number of gates! So, the approach is not completely crazy, but I agree that it's hard to propose accurate numbers on that topic. I hate to be a seagull (fly in, poop, fly away), but even though I'm not active in this spin, I need to know how the group arrived at the data used in the SoC slide you sent. Frankly, I don't buy it, and I don't think my company would, either! Again and again, everyone thinks that memory is the answer to all that "empty space" on silicon, but the actual numbers we see never align with that -- there's plenty of logic needs, and memory is more efficient when not encumbered by a logic process (and vice-versa). Our ASIC group sees a lot of SRAM, but it's never more than about half the chip, worst-case. All the new design wins we are getting indicates its the tightly integrated, fast logic that sells the high-end and medium-end volumes. Sure, on-chip memory will grow by 10x and more -- but 94% of the area? Reused logic <10% of the chip? C'mon!!! Please explain what I'm missing here -- this doesn't sound consistent to me. I was wondering the same thing. But then I wonder if they might have in mind that with the faster technologies that the new transistors will bring perhaps more functionality can be put in software vs. hardware and still be able to meet "real time" needs. Conclusion: no final result yet

5. ITRS 2000 Update Work In Progress - Do Not Publish! 5 SOC Low Power Total Power Trend with No Low Power Solution Total Power Trend with Low Power Solution Scenario to keep 3W Low Power ITRS, meeting in Leuven 1st draft

6. ITRS 2000 Update Work In Progress - Do Not Publish! 6 1st draft An overall DSM requirements table See tab.2-1-4-2 See tab.2-1-4-3 See tab.2-1-4-4 See tab.2-1-4-5 See tab.2-1-4-6 DSM (*a) Next Page (*b) Next Page (*c) Next Page (*d) Next Page ITRS, meeting in Leuven

7. ITRS 2000 Update Work In Progress - Do Not Publish! 7 - Definition of scope for “Design” ・ Does it mainly address hardware implementation technologies ? ・ It needs to include system integration, software technologies and embedded blocks (RF, analog, MEMS,) - Need “Design technology nodes” in addition design technology turning-points, for example ・ IP design ・ DSM related technologies ・ Power supply scheme Proposal or Concern on ITRS2000 and beyond

8. ITRS 2000 Update Work In Progress - Do Not Publish! 8 Proposal or Concern on ITRS2000 and beyond (cont'd) Results of recent discussions: Design TWG plans for a much more active role in the field of mixed signal design.

9. ITRS 2000 Update Work In Progress - Do Not Publish! 9 The Internet Sematech, GSRC “The Golden Copy” The World of the Living Roadmap Technology Models University Researchers Proprietary Models Firewall Richard Newton

10. ITRS 2000 Update Work In Progress - Do Not Publish! 10 Questions addressed in consultations with other TWGs Meeting with PIDs: Agreement to work together on numbers for power saving, gate leakage spec, benchmark circuits (analog and matching) Meeting with interconnect TWG: Agreement to cooperate on task force on parameter improvements for contact resistances (tungsten?), metal resistivities (copper?), and intermetal dielectric constants

11. ITRS 2000 Update Work In Progress - Do Not Publish! 11 Questions addressed in consultations with other TWGs (cont'd) Meeting with Test TWG, Assembly and Packaging: Design will review the frequency numbers in the tables based on inputs from Japanese roadmap