1. Additional Hardware Optimization m5151117 Yumiko Kimezawa October 25, 20121RPS

2. Outline Ethernet Additional Hardware Optimization Future Work October 25, 20122RPS

3. Ethernet Hardware part -Composition of necessary cores for handling Ethernet (Completion) -Compilation (Not completion) Software part - Changing software for transferring data with Ethernet (Not completion) October 25, 20123RPS

4. Ethernet Handling Ethernet is not easy I don’t have enough time… October 25, 2012RPS4 If I have extra time, I will deal with this task

5. Proposal of Optimization Pipeline processing on single CPU → Using hardware resources effectively Adding DMA controller → Data transfer is accelerated to high speed October 25, 2012RPS5 Signal Reading Filtering PPD Algorithm Signal Reading Filtering PPD Algorithm

6. Additional Hardware Optimization (Current Work) October 25, 2012 RPS 6 Change of existing hardware for executing pipeline processing -Using clock crossing bridge core -Dividing CPU memory into data memory and instruction memory -Implementing DDR2 SDRAM core instead of on-chip memory Graphic LCD Controller Data Mem Data Mem CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART LED Controller LED Controller Avalon Bus FIR Filter DDR2 SDRAM DDR2 SDRAM FPGA Clock Crossing Bridge ECG Data ECG Data Inst Mem Clock Crossing Bridge PLL SysID

7. SOPC Builder Window October 25, 2012RPS7

8. Future Work Minor change of software having single CPU -Until Nov. 1 Measurement of data transfer time between ECG data rom and filter, filter and memory and so on, and finding bottlenecks of data transfer -Until Nov. 8~16 Adding DMA controller module to BANSMOM for getting rid of the bottlenecks of data transfer -Until Nov. 16~23 October 25, 20128RPS

9. October 25, 2012RPS9 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Data Mem Data Mem Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA DMA controller ECG Data ECG Data Inst Mem Investigation of BANSMOM System -Need to divide Master CPU memory into inst. mem and data mem -Need to use off-chip memory