1. FE-I4 Chip Development for Upgraded ATLAS Pixel Detector at LHC Marlon Barbero, Bonn University (for the FE-I4 Collaboration) Pixel 2010, Grindelwald Switzerland, Sept. 6 th -10 th 2010

2. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 2 Content Upgrades: IBL / sLHC.  FE-I4, new ATLAS pixel Front-End for IBL & sLHC. FE-I4A overview. Analog pixel. Digital pixel and digital Double-Column. Milestones and conclusion.

3. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 3 FE-I4 for IBL & sLHC IBL (~2016): inserted layer in current pixel detector. Present beam pipe & B-Layer Existing B-layer New beam pipe IBL mounted on beam pipe FE-I4 - All Silicon. - Long Strips/ Short Strips / Pixels. - Pixels: - 2 or 3 fixed layers at ‘large’ radii (large area at 16 / 20 / 25 cms?) -2 removable layers at ‘small’ radii sLHC tentative layout (~2020): 4-5 pixel layers, small radii / large(r) radii (note: Discussion on boundary pixel / short strips, ID layout…). ATLAS Pixel Detector 3 barrel layers / 3 end-caps end-cap: z± 49.5 / 58 / 65 cm barrel: r~ 5.0 / 8.8 / 12.2 cm see F. Hügging, Monday Iourii Gusakov

4. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 4 Motivation to re-design the FE Need for a new FE? Smaller inner layer radius + potential luminosity increase  higher hit rate.  Current FE-I3 column-drain architecture saturated.  FE-I4 new digital architecture: local regional memories, (stop moving hits around unless RO).  FE-I4 has smaller pixel size (reduced cross-section).  Technology 130nm: Higher integration density for digital circuits, radiation-hardness (no Enclosed Layout Transistor), availability on timescales of our experiments. FE-I3  FE-I4 Hit prob. / DC Inefficiency [%] LHC IBL sLHC FE-I3 at r=3.7 cm! The “inefficiency wall” 100 80 60 40 20 0 0 0.5 11.522.5 3 3.5 4 4.55 0.25 μm  130 nm

5. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 5 Future Thin FE-I4-Based Module (& Consequences for FE-I4) FE-Chip Sensor Flex 1 1 2 2 3 3 4 1) Big chip (periphery on one side of module). 2) Reduce size of periphery (2.8 mm  2 mm). 3) Thin down FE chips (190 μm  90 μm). 4) Thin down the sensor (250 μm  200 μm)? 5) Less cables (powering scheme)? 5 Big FE (~2x2cm!) with increased active area: from less than 75 % to ~90 %:  Reduced periphery; bigger IC; cost down for sLHC (main driver is flip-chip costs per chip). No Module Controller Chip:  More digital functionality in the IC. Power:  Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  power routing. challenging: power (routing, start-up), clk. distrib., simulation / verification, yield 4 see L. Gonella, Thursday

6. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 6 Target Specifications for FE-I4 Rad.-hardness: >250 MRad ionizing dose (FE-I3: >50 Mrad). Minimal guidelines: no ELT, minimal size and guard rings only for analog & sensitive digital circuitry. DC leakage current tolerant to > 100 nA. ToT coded on 4 bits. FE-I3FE-I4 Pixel Size [μm 2 ]50×40050×250 Pixel Array18×16080×336 Chip Size [mm 2 ]7.6×10.820.2×19.0 Active Fraction74 %89 % Analog Current [μA/pix]2610 Digital Current [μA/pix]1710 Analog Voltage [V]1.61.4 Digital Voltage [V]21.2 pseudo-LVDS out [Mb/s]40160 biggest in HEP to date analog / digital power tuned for IBL occupancy

7. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 7 FE-I4A FE-I4A: – Full scale prototype. – Many test features provided. – Submitted August 2010. – Wafer ship date September 14 th. Test pads 336×80 pixel array Periphery IO pads 16.8 mm 2 mm 20.2 mm

8. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 8 pixel array: 336×80 pixels periphery digital 4-pix (PDR) analog 1-pix (FEND) 4-pixel regionEODCL DDC & DC PowerDOBEOCHLPadsCLKGENCMD DCDCNFGREGDACsCREF StopMode, CalPuls, InMUX, EFUSE, AltComp… + Integration & Verification IOMux+ Bypass

9. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 9 Analog Pixel In FE-I4_proto1 (FE-I4 prototype submitted in 2008): 2-stage architecture optimized for low power, low noise, fast rise time.  regul. casc. preamp. nmos input.  folded casc. 2 nd stage pmos input.  Additional gain, Cc/Cf2~6.  2 nd stage decoupled from leakage related DC potential shift.  Cf1~17fF (~4 MIPs dyn. range). 13b configuration:  4 FDAC: tuning feedback current.  5 TDAC: tuning of discriminator threshold.  2 Local charge injection circuitry.  1 Hit Enable.  1 HitBus / IleakMonitor 50  m 150  m Preamp Amp2 FDAC TDAC Config Logic discri

10. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 10 Noise and Radiation Results a)ENC on “Collaboration Proto 1” before and after irradiation (200 Mrad) b)Measured ENC for pixels with and without C load c)Simulated ENC and time-walk @ 10 µA/pixel (preamp-amp2-comparator) ENC @ Low Current (10µA) (loaded ~400 fF) ~ 65 e ~ 90 e (10 µA) 200Mrad, C load ~400fF a) b) c) 20 ns timewalk for 2 ke - < Qin < 52 ke - & threshold @ 1.5 ke - ENC=160e- @ C d =0.4pF & I L =100nA ENC[e - ] C d [F] Q in [C] t LE [s] 100f200f300f 60 100 150 10k 20k30k40k I L = 0 nA 20n 10n 0 I L =100 nA

11. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 11 Digital Pixel: Regional Architecture local storage Store hits locally in region until L1T. Only 0.25% of pixel hits are shipped to EoC  DC bus traffic “low”. Each pixel is tied to its neighbors -time info- (clustered nature of real hits). Small hits are close to large hits! To record small hits, use position instead of time. Handle on TW. low traffic on DC bus Consequences: Spatial association of digital hit to recover lower analog performance. Lowers digital power consumption (below 10 μW / pixel at IBL occupancy). Physics simulation  Efficient architecture. disc. top left disc. bot. left disc. top right disc. bot. right 5 ToT memory /pixel 5 latency counter / region hit proc.: TS/sm/big/ToT Read & Trigger Neighbor Token L1TRead Digital Region 4-Pixel Unit

12. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 12 Performance / Efficiency IBL: charge sharing in Z comparable to phi Memories SimulationAnalytical IBL10xLHCIBL10xLHC 5 0.047%2.19%0.029%2.25% 6 0.011%0.65%0.003%0.57% 7 <0.01%0.16%<0.01%0.13% η=0 Mean ToT = 4 0.6% Regional Buffer Overflow @ IBL rate, pile-up inefficiency is the dominant source of inefficiency Inefficiency: Pile-up inefficiency (related to pixel x-section and return to baseline behavior of analog pixel)  ~ 0.5%. Regional buffer overflow  ~0.05%. Inefficiency under control for IBL occupancy.

13. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 13 Pixel Layout Note: Digital ground tied to substrate, mixed signal environment BUT digital region placed in “T3” deep n-well. Preamp Amp2 FDAC TDAC Config Logic discri 50  m 250  m synthezised digital region (1/4 th )

14. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 14 Test Chip Submission FE-I4-P1 LDO Regulator Charge Pump Current Reference DACs Control Block Capacitance Measurement 3mm 4mm 61x14 array SEU test IC 4-LVDS Rx/Tx ShuLDO +trist LVDS/LDO/10b-DAC turboPLL : PLL core + PRBS + 8b10b coder + LVDS driv low power discri.

15. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 15 Schedule and more information Schedule: – FE-I4A submitted beginning August 2010. – FE-I4A end September 2010. – Test setup readiness ramping-up, on time for IC back. – Tests: Wafer, single-chip, bump-bonded (planar, 3D, diamond), irrad… Few references: – “Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC”, M. Karagounis et al, proceedings of TWEPP 2008. – “Design and Measurements of SEU tolerant latches”, M. Menouni et al, proceedings of TWEPP 2008. – “New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity”, M. Barbero et al, NIM A 604 (2009). – “Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity”, D. Arutinov et al, IEEE Trans. Nucl. Sci. 56, 388 (2009). – “An Integrated Shunt-LDO Regulator for Serial Powered Systems”, M. Karagounis et al, Proceedings of the 35th European Solid-State Circuits Conference, 2009. – “Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS”, A. Kruth et al, Proceedings TWEPP 2009. – “Low Power Discriminator for ATLAS Pixel Chip”, M. Menouni et al, proceedings of TWEPP 2009. – “FE-I4 ATLAS Pixel Chip Design”, M. Barbero et al, Proceedings of Science, Vertex 2009. see M. Backhaus, Poster Thursday plan for FE-I4B (= FE-I4 for IBL) in fall 2011

16. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 16 FE-I4A Collaboration Collaborate remotely using Cliosoft.com platform. Participating institutes: Bonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth, M. Karagounis. CPPM: D. Fougeron, F. Gensolen, M. Menouni. Genova: R. Beccherle, G. Darbo. LBNL: S. Dube, D. Elledge, J. Fleury (LAL), M. Garcia-Sciveres, D. Gnani, F. Jensen, A. Mekkaoui. NIKHEF: V. Gromov, R. Kluit, J.D. Schipper, V. Zivkovic. 160 18 FE-I3 FE-I4A

17. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 17 backup BACKUP SLIDES

18. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 18 pixel array: 336×80 pixels 4-pixel region periphery + Integration + Verification analog synthesized synthes -ized analog synthes -ized analog synthes -ized analog digital analog

19. From DC to FIFO DC 6b Region Add 8b Data 20b Hamming Decoder From Columns Event Builder Hamming Encoder Data Switch Read out Control Header Fifo 8 places 3 * 12 Bit Word 0 Word 1 Word 2 8 Bits12 Bits 36 Bits Read Busy WriteFull ServiceRead Back

20. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 20 Zoom1 Test pads 250×50µm 2 pixel ~150×50µm 2 analog pixel 4-pixel PDR Alignment mark Double-Column 0 DC bus

21. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 21 Zoom3 EOCHL DOB CLKGEN IOMUX CMD DCD CNFGREG IO pads

22. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 22 Yield Estimated from: – Small analog test chips. – 8 fully tested wafers of Medipix 3 ICs, assuming same defect density for synthesized logic. Expect of order ~39% digitally perfect chips. Yield enhancement: – Triple redundant read tokens. – Hamming coded pixel data and address (w. minimal # of gates). – Redundant configuration shift register.  Fully functional chips yield might be as high as 76%. (with isolated dead pixels at level <0.1%).

23. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 23 Preamp. & Leakage Compensation I_leakage compensation Cst I feedback Regulated cascode preamp.  high gain.  less crosstalk path through biasing voltage. Triple well NMOS input.  shield from substrate noise. Feedback capacitor discharged by NMOS feedback transistor. Leakage current compensation scheme based on differential amplifier. 2ke<Qin<22ke 100nA leakage  10mV DC shift Vout[V] t[s] Vout[V] t[s] 200m 250m 225m 0.1  0.5  0.1  0.5  200m 300m 380m

24. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 24 2 nd stage & Comparator PMOS input folded regulated cascode (straight cascode in futur?). Negative going output. Classic 2-stage comparator. 20ns timewalk for 2ke - < Qin < 52ke - & threshold @1.5ke - ENC=160e- @ Cd=0.4p & Il=100nA ENC[e - ] Cd[F] Qin[C] t LE [s] 100f 200f300f 60 100 150 10k20k30k40k Il=0nA 20n 10n 0 2 nd stage amplif. Discriminator Il=100nA

25. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 25 Clock Multiplier For IBL, need to transmit data out at BW of 160Mb/s 2 options: – send a 80MHz CLK to the FE and use both edges to transmit Needs modification of BOC / ROD to produce higher speed TTC Needs synchronization protocol on the FE between 80MHz clock & beam crossing. A new DORIC needs to decode CLK at twice frequency – send a 40MHz CLK to the FE and multiply clock on FE Needs a clock multiplier on chip Note: synergy with what the strip MCC need In FE-I4, we will provide both options: – Clock multiplier from the 40MHz input clock – AUX: possibility to send the 80MHz to the FE I/O choices for ATLAS IBL, ATLAS Pixel System Design Task Force

26. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 26 PLL Overview Charge Pump Voltage Controlled Oscillator Phase Frequency Detector Frequency Divider Loop Filter Conversion and Buffering 40 MHz 640 MHz

27. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 27 8b10b encoder For IBL, need to transmit data out at BW of 160Mb/s At BOC/ROD: – Data rate 4 times the clock rate – Phase adjustment Use Clock Data Recovery mechanism CDR requires an output data stream with good engineering properties 8b10b: – adequate for this purpose, enough transitions for reliable CDR – widely used  easy to implement – provides some level of error detection – provides comma for frame identification & synchronization I/O choices for ATLAS IBL, ATLAS Pixel System Design Task Force

28. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 28 SEU-hardened latch CPPM has studied the influence of various layout of a DICE latch on the SEU x-section. Latch5.1 and latch5.2 ; Area :12µm × 4µm = 48 μm 2 nMos separation : 7µm ; pMos separation : 3 µm Physical separation of sensitive node pairs. Calin et al, IEEE Trans. Nucl. Sci. vol43, n.6, 1996 1.a 1.b 2.a 2.b 3.a 3.b 1.a 1.b 2.a 2.b 3.a 3.b Triple Redundant Logic with Interleaved Layout. X-section [cm 2.bit -1 ]: - Standard Latch: ~ 5.10 -14 - DICE w. improved layout: ~ 3.10 -16 X-section : < 1.10 -17

29. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 29 Pixel occupancy  Data bandwidth Pixel hit rate  FE output bandwidth: – # bits / pixel transmitted? » address 7+9 bits, analog info 4+2 bits  22b? » data output protocol? Reduce data output by taking into account clustered nature of real physics hits. NUMBER OF PIXELS FE-I4, central module, 21cm layer FE-I4, central module, 3.7cm layer 10xLHC FE-I4, central module, 3.7cm layer 3xLHC

30. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 30 Pixel occupancy  Data bandwidth Example 3: clustered data out with fixed format. compression factor (all at 3×LHC) 3.7cm (vs. 21cm), η=0 indiv pixels: 4.09 (0.25)×(7+9+4+2)= 1.00 (1.00)A.U. static 1×2: 3.45 (0.18)×(7+8+2×4+2)=0.96 (0.83) A.U. dynamic 1×2: 3.02 (0.15)×(7+9+2×4+2)= 0.87 (0.74) A.U. static 1×4: 2.86 (0.17)×(6+8+4×4+4)=1.08 (1.08) A.U. dyn. in-DC 1×4: 2.43 (0.15)×(6+9+4×4+4)= 0.95 (0.95) A.U. dynamic 1×4: 2.13 (0.14)×(7+9+4×4+4)= 0.85 (0.94) A.U. DC(×40) row (×336) column rowToT NL assumption: 100kHz L1T, 336×80 pixels FE-I4 Disclaimer: no header, trailer, DC-balancing, error correction… 10 6.count.FE -1.s -1 preliminary

31. Marlon Barbero, FE-I4 Chip, Pixel2010, Grindelwald Switzerland, Sept. 7 th 2010 31 Output data protocol 24-bit Record Word Acro -nym Field 1Field 2Field 3Field 4Field 5Comments Data Header DH11101001xxxx [3:0] trigID [7:0] bcID xxxx reserved for later use Data Record DR [6:0] Column [8:0]Row [3:0] ToTtop [3:0] ToTbot Column numbering: 0000001 to 1010000 Address Record AR11101010Type [14:0] Address Type 0: Global Register / Type 1: Shift Register Position Value Record VR11101100 [15:0] Value Value Record without previous Address Record allowed Service Record SR11101111 [15:0] Message Service Message (e.g. error codes) Empty Record ER00000000 Idle = K.28.1 commas (8b10b coding case) 8b10b frame: SOF (K.28.7), followed by 24 bits record word(s) and an EOF (K.28.5) + idle (K.28.1) Table: possible data words