1. Introduction ProjectRequirements Project Requirements In a previous senior design project, a wireless front-end was added to Iowa State University’s Teradyne J750 high-speed Radio Frequency tester. This provided the J750 with the potential to wirelessly test digital logic chips. However, one of the unresolved issues is the lack of the ability to pass a clock signal from the J750 to the wireless interface. Without a clock signal, the two devices have no way to synchronize data transitions. A clock training signal can be sent by the Teradyne J750 & can be recovered by the interface’s PLL (Phase Lock Loop). Send/Receive network transmits up to at least five feet. Phase difference between Teradyne J750 clock and received clock is not greater than the overall clock signal. The Teradyne tester is temperature sensitive. It must operate within 3 degrees of calibrated temperature. Maximum data transfer: 115.2kbs, set by Send/Receive network. May only use 1 field programmable gate array (FPGA) for data processing. Send/Receive network operates at only one frequency: 915MHz. Team Information Team Members Matt DahmsEEmcdahms@iastate.eduFaculty Advisor Client May 06-15 Joe ChongoEEjchongo@iastate.eduDr. Robert J. Weber ISU ECpE Department Justine SkibbeEEjskibbe@iastate.edu Those with knowledge of EE and/or CprE. Must have previous experience with using the Teradyne J750. Abstract AssumptionsLimitations UsersUses Problem Statement The goal of this project is to assess the different options of recovering the clock signal at the wireless interface and implement the most viable recovery option. This function will be added to the existing wireless tester. When fully implemented, the device would be capable of operating in a completely wireless environment. This will be done by integrating a clock recovery circuit consisting of an NRZ/RZ converter and a Phase Locked Loop (PLL) with the previously developed interface components. Operating Environment The J750 is sensitive to temperature & humidity: must operate at +/- 3°C of calibrated temperature. Interface will operate indoors near a wall outlet. System is sensitive to electro-static discharge and should be handled while wearing an ESD wristband. Interface should not be used around wireless signals generating frequencies around 915MHz for risk of interference. To test a digital device wirelessly for functionality. An independent interface between the Teradyne tester and wireless interface for digital I/O chips. The wireless interface will be able to recover a clock signal generated and process test data transmitted by the Teradyne tester. A demo test of a digital chip using the Teradyne J750 and the completed wireless interface. A reference manual that will be updated to include how to remotely test a device and properly recapture the clock signal using the Teradyne J750. Design Objectives Must be simple to setup. Software must be user friendly. Wiring must be clean and safe. Functional Requirements Must be able to transmit clock & data wirelessly from Teradyne tester to interface. Interface must be able to replicate the clock signal. Interface must be able to process test data. Interface must present data to device under test (DUT) and present reply to the Teradyne J750. Design Constraints Printed circuit board should be small & manageable. Design should be cost effective. Interface should be powered via wall outlet, batteries, or a combination of both. Measurable Milestones Design & test clock recovering circuitry. Write new control code for FPGA. Successful recovery of clock by interface. Mount circuitry on printed circuit board. Integrate clock recovery circuit with existing interface. Approach & Considerations Proposed Approach Technologies Considered Research potential technologies Write necessary control code Design/Build prototype Integrate with existing interface Non return-to-zero to return-to-zero converter (NRZ/RZ) Clock recovering mechanism Phase locked loop (method chosen) Manchester Encoder/Decoder Control code for FPGA Verilog (method chosen) VHDL Lab testing of NRZ/RZ converter Lab testing of phase locked loop Full clock recovery testing Final system testing Intended Users & Uses Assumptions & Limitations End-Product Description Testing Considerations Resources & Schedule Closing Summary In today’s ever expanding technology dependent society, the general movement is toward wireless devices. These devices must have their RF capabilities tested. The ECpE department at ISU has a Teradyne tester which tests digital I/O and a previous group has created the wireless interface to communicate with the tester. It does not, however, have the capability to send its clock signal wirelessly from the tester. Finishing this outstanding design implementation will make this wireless interface exclusively wireless and open up new doors of research and testing to ISU’s Teradyne users. Estimated Personal Time Efforts * Srisarath Patneedi is no longer with the team – on Co-op Project Schedule Financial Resources 267 271 294 78 Teradyne J750 Tester Send/Receive Network FPGA Wireless Interface with J750 Proposed Block Diagram of Final Implementation