1. COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency 1/17/2016Page 1XCube 2011

2. COTS EW/Radar Development Platform 1/17/2016 XCube 2011Page 2 Adarate FPGA Front end & analog interface (ADC/DAC) NVIDIA Floating point DSP & HMI - GPGPU GTX590 Adapteva (future) Complex CPU/DSP intensive processing - ATDSP (future) / Others Data Storage and Control XCube Development Platform - Control / Record / Replay Software - Dual Xeon CPU - Up to 144GByte Memory - >4.4GByte/s Throughput - >8 GByte/s Burst - 96TB removable storage (shown) - Virtex6 130LXT – 475SXT - 2x National ADC083000 (selectable) - 2x Analog devices AD9739 - 2x 1Gbit Ethernet - PCI-express

3. Other Demo Setup (LPI Radar Simulation & Detection) 1/17/2016XCubePage 3 Signal Generator Receiver ADC FPGA Frontend Stream Buffers Disk Scheduler Disk Manager Control PC PCI e GP-GPU Transmit DAC HRFT Standalone HRFT Internal disk Processor Array (future FMC) disk Disk writer Tight Timing High Throughput Disk writer DMA Decoupling Buffering and ProcessingExternal Interfaces Host Processing 2.4Gsps - 8 bit data 8 Channels 150MHz (I/Q-data) Window FFT waterfall 1200MByte/s throughput (and storage) Radar (FMCW) / Frequency Hop (FH) Interface Manager