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Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding Karkooti, M.; Cavallaro, J.R.; Information Technology: Coding and Computing, 2004.

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Presentation on theme: "Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding Karkooti, M.; Cavallaro, J.R.; Information Technology: Coding and Computing, 2004."— Presentation transcript:

1 Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding Karkooti, M.; Cavallaro, J.R.; Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on, Volume: 1, April 5-7, 2004 Pages:579 - 585

2 Outline  Introduction  Algorithms Comparison  Scaling factor  BFU (Bit function unit)  CFU (Check function unit)  Quantization  Conclusion

3 Introduction  (3,6) LDPC codes  Min-sum algorithm  Parity check matrix is generated by shifting

4 Algorithms Comparison AlgorithmAdditionFunctionShift Log-Sum-Product24(N-K)+7N12(N-K)-- Min-Sum24(N-K)+7N-- Mod. Min-sum24(N-K)+10N--6N

5 Comparison  N is codeword length  K is message bits  W c is column weight  W r is row weight  b is the number of the bits per message  S is the folding factor

6 Modified (Scaling)  Scaling factor of 0.8 is optimal for (3,6) LDPC code.  Scaling the soft info. not only compensates for loss of performance, but also results in superior performance.

7 Architecture  Channel value are stored in MEMInit n  Iteration result are stored in MEMCode mn  Message are stored in MEM mn

8 BFU  Scaling Factor: 0.5+0.25=0.75~=0.8  Can be modified for irregular LDPC code

9 BFU to Memories  S/M: split and merge unit  ADGB: Address generator for BFU

10 CFU  Out i =min{abs(in i ’ )|i ’ !=i}  Min: Output will be minimum input  SM->2 ’ s:Sign- magnitude to 2 ’ s complement presentation

11 CFU to Memories  S/M: split and merge unit.  ADGC: Address generator for CFU

12 Quantization  Sign + integral + fraction=1+2+2= 5 bits

13 Cost ResourceUsedUtilization Rate Slices1135279% 4-input LUTs2037471% Bonded IOBs10014% Block RAMs6668%

14 Throughput  N=1536 K=768, S=16, μ=20  1536/16=96BFUs768/16=48CFUs  For a LDPC code with the block length of 1536 bits, the decoder achieves a data rate of up to 127Mbps.

15 Conclusion  Overflow issue  Scaling factor & LLR  Simultaneously multiple access  Pack message  Reduce interconnection complexity  Partition parity check matrix


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