1. Microelectronic Systems--University of Tennessee 1 1 Mancala Ben McCue Nithiya Gajanetharan Nora D. Bull ECE 551

2. Microelectronic Systems--University of Tennessee 2 2 Background One of the oldest games known to man African and Asian societies play this game as a form of chess Some alterations made to original rules to make compatible with FPGA board.

3. Microelectronic Systems--University of Tennessee 3 3 Background Goal: –Capture more seeds than opponent. Original rules: –Select hollow on your side of the board and sow seeds around board until you run out. –Place seeds in your home but skip opponent’s home as you pass by. –After first player releases last seed - second player’s turn begins. –If player runs out of seeds on their side of the board then game is over and the other player receives all seeds left on their side. http://www.mastersgames.com/rules/mancala-rules.htm http://en.wikipedia.org/wiki/Mancala

4. Microelectronic Systems--University of Tennessee 4 4 FPGA Rules To pick where to start use push buttons to select 1-4 or 5-8 holes –Player 1 can only select 1-4 –Player 2 can only select 5-8 Switch 1* sets side of board player is selecting from –If switch is up: 5-8 –If switch down: 1-4 FPGA board will keep up with amount of seeds in homes

5. Microelectronic Systems--University of Tennessee 5 5 FPGA Rules How to tell if it is your turn: –If LED 1 on then Player 1’s turn –If LED 2 on then Player 2’s turn Keeping Score: –To display Player 1’s score on seven segment LED switch 2* needs to be down –To display Player 2’s score on seven segment LED switch 2* needs to be up

6. Microelectronic Systems--University of Tennessee 6 6 Design Flow

7. Microelectronic Systems--University of Tennessee 7 7 Applying to FPGA

8. Microelectronic Systems--University of Tennessee 8 8 Graphical Interface

9. Microelectronic Systems--University of Tennessee 9 9 Graphical Interface

10. Microelectronic Systems--University of Tennessee 10 Module Description State Machine Built in Self Test (BIST) Display Module (7-Seg Led’s) Data Input (Switches, Buttons) Computational Logic Sample Clock Clock Divider Debounce Module