1. CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-1 Design Procedure 1Created by: Ms.Amany AlSaleh

2. 2 Overview  Part 1 – Design Procedure Steps 1.Specification 2.Formulation 3.Optimization 4.Technology Mapping 5.Verification Manual Simulation Beginning Hierarchical Design Technology Mapping - AND, OR, and NOT to NAND or NOR Created by: Ms.Amany AlSaleh

3. 3 Overview (continued)  Part 2 – Combinational Logic Functions and functional blocks Rudimentary logic functions Decoding using Decoders Implementing Combinational Functions with Decoders Encoding using Encoders Selecting using Multiplexers Implementing Combinational Functions with Multiplexers Created by: Ms.Amany AlSaleh

4. 4 Combinational Circuits  A combinational logic circuit has: A set of m Boolean inputs, A set of n Boolean outputs, and n switching functions, each mapping the 2 m input combinations to an output such that the current output depends only on the current input values.  A block diagram: m Boolean Inputs n Boolean Outputs Combinatorial Logic Circuit Created by: Ms.Amany AlSaleh

5. 5 Design Procedure  Specification Write a specification for the circuit if one is not already available. Determine and name inputs. Determine and name outputs.  Formulation (Truth table) Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification.  Optimization Simplify the resulting Boolean functions for each output. Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters. Created by: Ms.Amany AlSaleh

6. 6 Design Procedure  Technology Mapping (Section 3-4) Map the logic diagram or netlist to the implementation technology selected. Transform the logic diagram to a new diagram using the available implementation technology.  Verification (Section 3-6) Verify the correctness of the final design manually or using simulation. Created by: Ms.Amany AlSaleh

7. 7 Example-1 Design a combinational circuit with 3 inputs and 1 output. The output must be logic 1 when the binary value of the inputs is less than 011(3) and logic 0 otherwise. Use only NAND Gates. Created by: Ms.Amany AlSaleh

8. 8 Example-1 (Cont)  Optimization: Boolean Function for each output F = X’Y’ + X’Z’  Logic Diagram and Technology Mapping  Specification: 3 inputs : X, Y and Z 1 output: F  (Formulation) Truth Table 3 inputs  2 3 rows Created by: Ms.Amany AlSaleh

9. 9 Example-2 Design a BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word Created by: Ms.Amany AlSaleh

10. 10 BCD-to-Excess-3 Code Converter BCD codeExcess-3 code 00000000 11001100 11101110 01010101 Example-2 (Cont.) In multiple output circuits, each output must be expressed separately as a function of all the input variables Created by: Ms.Amany AlSaleh

11. 11  Specification: 4 Inputs: A, B, C and D 4 Outputs: W,X, Y and Z Don’t cares: BCD 1010 to 1111  Formulation (Truth Table) 4 inputs  2 4 rows BCD only needs 10 rows Design of a BCD-to-Excess-3 Code Converter Example-2 (Cont.) W=  (5,6,7,8,9) X=  (1,2,3,4,9) Y=  (0,3,4,7,8) Z=  (0,2,4,6,8) Created by: Ms.Amany AlSaleh

12. 12  Optimization Boolean function for each output using K-maps. B C D A 0132 4576 12131514 891110 1 11 1 XXX XX X 1 B C D A 0132 4576 12131514 891110 11 1 1 XXX XX X 1 B C D A 0132 4576 12131514 891110 11 1 XXX XX X 1 1 w y x Example-2 (Cont.) W=  (5,6,7,8,9) X=  (1,2,3,4,9) Y=  (0,3,4,7,8) Z=  (0,2,4,6,8) B C D A 0132 4576 12131514 891110 1 11 1 XXX XX X 1 z W= A + BC + BD = A + B(C+D) X = B’C + B’D + BC’D’ = B`(C+D) + BC`D` Y = CD + C’D’ Z = D’ Created by: Ms.Amany AlSaleh

13. 13 Example-2 (Cont.)  Draw the logic diagram W= A + B(C+D) X = B`(C+D) + BC`D` Y = CD + C’D’ Z = D’ Created by: Ms.Amany AlSaleh

14. 14 Design a BCD-to-Seven-Segment Decoder.  A BCD-to-seven-segment-decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate output for the selection of segments that display the decimal digit.  Each digit is formed from 7 segments, each consisting of 1 LED that can be illuminated by digital signals. Example 3 Created by: Ms.Amany AlSaleh

15. 15 BCD code 11111111111111 BCD-to-7-Segment Decoder 00010001 Example 3 (Cont.) 1.Specification:   4 Inputs (BCD bits): A, B, C and D  7 Outputs (display segments): a, b, c, d, e, f and g  Don’t cares: BCD 1010 to 1111, can we really have them as don’t cares? g f e d c b a A B C D Created by: Ms.Amany AlSaleh

16. 16 Example 3 (Cont.) 0a,b,c,d,e,f 1b,c 2a,b,d,e,g 3a,b,c,d,g 4b,c,f,g 5a,c,d,f,g 6a,c,d,e,f,g 7a,b,c 8a,b,c,d,e,f,g 9a,b,c,d,f,g a b c g e d f  List the segments that should be illuminated for each digit. Created by: Ms.Amany AlSaleh

17. 17 2. Formulation (Truth table) : 2. Formulation (Truth table) To display the input BCD digit :  Which segment(s) should illuminate (be turned on)?  Which segment(s) should not illuminate (be turned off)? a b c d e f g Example 3 (Cont.) Created by: Ms.Amany AlSaleh

18. 18 3. Optimization: 3. Optimization: Boolean Function for each output  a=? b=? c=? d=?  e=? f=? g=? 4. Draw the logic diagram Example 3 (Cont.) Created by: Ms.Amany AlSaleh