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Course: High-Speed and Low- Power VLSI (97.575) Professor: Maitham Shams Presentation: Presentation: True Single- Phase Adiabatic Circuitry By Ehssan.

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Presentation on theme: "Course: High-Speed and Low- Power VLSI (97.575) Professor: Maitham Shams Presentation: Presentation: True Single- Phase Adiabatic Circuitry By Ehssan."— Presentation transcript:

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2 Course: High-Speed and Low- Power VLSI (97.575) Professor: Maitham Shams Presentation: Presentation: True Single- Phase Adiabatic Circuitry By Ehssan Hosseinzadeh Special Student

3 Outline Introduction Adiabatic – Switching Circuits True Single-Phase adiabatic Circuit Results Conclusion References

4 Introduction Importance of Reducing Power Dissipation Techniques =>Parallelism => Pipeline => Transformation => Reduce the Chip wide Supply voltage => Energy Recovery

5 Conventional Energetic Swinging voltage on capacitor: - Zero => V -V => Zero Engergy dissipation per transition E= ½ CV 2 Adiabatic - Switching Circuits

6 Recovery Energy Adiabatic - Switching Circuits E diss = P. T = I 2. R.T = (RC/T) CV 2

7 True Single-Phase adiabatic Circuit Different Approaches: Signal voltage swing > Vt of CMOS => Adiabatic Amplification Dynamic logic families => 2N2P, 2N-2N2P, => True Signle-Phase Energy-Recovery Logic (TSEL) => Source–Coupled Adiabatic Logic (SCAL)

8 True Single-Phase Energy-Recovery Logic (TSEL) Cascades are composed of alternating PMOS and NMOS gates TSEL GATES True Single-Phase adiabatic Circuit

9 PMOS DP: Vpc: H-L Vpc  VRP - |vtp| EP: Vin: H, Vpc:L Vpc < VRP - |vtp| Ddp > |Vtp| Vpc  VRP - |vtp| NMOS EN: Vpc > VRN + |vtn| CN: Vpc  VRN + |vtn|

10 TSEL Cascades TSEL Cascades are built by stringing together alternating PMOS and NMOS gates

11 SCAL Gates Single Phase power Clock Operation Tunable Current Source at each Gate

12 Vpc Vbp Vbn DP: Vpc: H-L Adiabatlically till Vpc > |Vtp| EP: Vpc: L-H Vbp increase Vdd - |Vbp| > |Vtp| Vpc < Vxp - |Vtp| Dpp > |Vtp| Vpc > Vxp - |Vtp|

13 SCAL Cascades

14 Results 8-bit Carry-Lookahead adder (CLAs) Developed in Static CMOS, PAL, 2N2P, TSEL, SCAL (0.5um) Freq: 10 –200 MHz SCAL CLA => 1.5 – 2.5 times more efficient than PAL, 2N2P SCAL CLA => 2 – 5 times less dissipative than purely combinational or pipelined CMOS

15 Conclusion True Single-phase adiabatic logic family: TSEL, SCAL Source-coupled variant of TSEL => Increase energy efficiency by using tunable current source Avoid the problems: Multiple Power-clock schemes - Increased energy dissipation - Layout Complexity in clock distribution, - Clock Skew - Multiple power–clock generator

16 References True Single Phase Adiabatic Circuitry, Suhwan Kim and Mario Papaefthymiou Energy Recovery For Low Power CMOS, WC Athas and N. Tzartanis Low Power Digital Systems Based on Adiabatic-Switching Principles, William C. Athas

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