1. ELE 523E COMPUTATIONAL NANOELECTRONICS W10: Defects and Reliability, 16/11/2015 FALL 2015 Mustafa Altun Electronics & Communication Engineering Istanbul Technical University Web: http://www.ecc.itu.edu.tr/

2. Outline  Defects in nanoscale  Permanent defects  Transient defects  Defects in logic gates  Bayesian networks for defect modeling  Defects in nano arrays  Defect tolerance in nano arrays

3. Defects  Defects are the main headache in nanoscale.  Up to 10% defect ratio  Defects are inevitable and must be handled Defects in self-assembled nano arrays

4. Defects Permanent  Happens before first usage.  Happens mostly in the fabrication and packaging level.  Results in hard error.  Relatively easier to fix  Detecting the defect followed by reconfiguration. Transient  Happens any time.  Result in hard error.  Result in soft error.  Random defects are harder to fix.  The only way is redundancy.  Dummy devices added. 1 1 AND 0 at t=2s 1 at t=10s Soft error 1 1 AND 0 at t=0s 0 at any time Hard error

5. Soft Defects in Gates 0 0 AND 0 Error probability : a gate evaluates the incorrect result, the complement of the correct Boolean value, with. 0 1 AND 0 1 0 0 1 1 1 Ideally With a defect 0 with a probability of 1- 1 with a probability of 1 with a probability of 1- 0 with a probability of

6. Soft Defects in Gates Error probability : each gate evaluates the incorrect result, the complement of the correct Boolean value, with. Example: What is the probability Px that the circuit produces an incorrect result. a b c x AND OR Px = - (2 2 - )c

7. Soft Defects in Gates Error probability : each gate evaluates the incorrect result, the complement of the correct Boolean value, with. Example: What is the probability Py that the circuit produces an incorrect result. a c b c y AND OR Py = 3 - 5 2 + 2 3 - ( - 2 2 )(a+b)c + (2 2 - 4 3 )abc

8. Soft Defects in Gates Px = - (2 2 - )c Py = 3 - 5 2 + 2 3 - ( - 2 2 )(a+b)c + (2 2 - 4 3 )abc Both circuits, A and B, implement the same Boolean function (a+b)c. Which circuit is better in defect tolerance? A B

9. Bayesian Networks for Errors  A, B, C, D, and E can be any circuit part.  Suppose that A, B, C, D, and E are gates.  P(A): Probability that there is an error at the output of A, i.e., the output of A is incorrect.  P(B|A): Probability that the output of B is incorrect, given that the output of the gate A is incorrect.  P(E|A,C): Probability that the output of E is incorrect, given that the output of the gates A and C are both incorrect. One-directional Bayesian network to model errors/defects in circuits

10. Defects in Nano Arrays Ideally f = A B + C D Each crosspoint is either closed (diode connected) or open. What if a crosspoint is closed when it is supposed to be open? What if a crosspoint is open when it is supposed to be closed? With a defect f = A B + B C D With a defect f = A + C D How to tolerate defects?

11. Defects in Nano Arrays Ideally f = (A B + C D) With a defect f = 0 How to tolerate defects? Each crosspoint is either closed (MOS or shorted) or open. What if a crosspoint is closed when it is supposed to be open?

12. Defects in Nano Arrays Each crosspoint is either closed or open depending on the applied literal. What if a crosspoint is always closed when it is supposed to switch? What if a crosspoint is always open when it is supposed to switch? Ideally f = x 1 x 2 x 3 + x 1 x 4 + x 2 x 3 x 4 + x 2 x 4 x 5 + x 3 x 5 0 1 With a defect f = x 1 x 2 x 3 + x 1 x 4 + x 2 x 3 x 4 + x 2 x 4 x 5 + x 3 x 5 With a defect f = x 1 x 2 x 3 + x 1 x 4 + x 2 x 3 x 4 + x 2 x 4 x 5 + x 3 x 5 How to tolerate defects?

13. Tolerating Defects in Nano Arrays  OFF-to-ON defect: The switch is ON when it is supposed to be OFF; x 1 =0.  ON-to-OFF defect: The switch is OFF when it is supposed to be ON; x 1 =1.  Each switch of the lattice has independent defect rates.

14. Tolerating Defects in Nano Arrays  Ideally, if x 1 =0 then all the switches are OFF.  Ideally, if x 1 =1 then all the switches are ON.  We use redundancy in tolerating defects powered by percolation.

15. Percolation Theory Rich mathematical topic that forms the basis of explanations of physical phenomena such as diffusion and phase changes in materials. Broadbent & Hammersley (1957).

16. Percolation Theory Sharp non-linearity in global connectivity as a function of random local connectivity.

17. Percolation Theory p 2 versus p 1 for 1×1, 2×2, 6×6, 24×24, 120×120, and infinite size lattices.  Each square in the lattice is colored black with independent probability p 1.  p 2 is the probability that a connected path exists between the top and bottom plates.

18. Margins  One-margin: Tolerable p 1 ranges for which we interpret p 2 as logical one.  Zero-margin: Tolerable p 1 ranges for which we interpret p 2 as logical zero. Margins correlate with the degree of defect tolerance.

19. Implementing Boolean Functions signals in: x i ’s signals out: connectivity top-to-bottom / left-to-right.

20. An Example with 16 Boolean Inputs A path exists between top and bottom, f L = 1

21. Margin Performance with a 2×2 Lattice f L =x 1 x 3 +x 2 x 4 g L =x 1 x 2 +x 3 x 4 Different assignments of input variables to the regions of the network affect the margins.

22. One-margins (always good) Defect probabilities exceeding the one-margin would likely cause an (1→0) error. f L =1f L =0 ONE- MARGIN

23. Good Zero-margins Defect probabilities exceeding zero-margin would likely cause an (0→1) error. f L =0 f L =1 ZERO- MARGIN

24. Poor Zero-margins Assignments that evaluate to 0 but have diagonally adjacent assignments of blocks of 1's result in poor zero-margins f L =0 f L =1 POOR ZERO-MARGIN

25. Lattice Duality A necessary and sufficient condition for good error margins is that the Boolean functions f L and g L are dual functions.

26. Lattice Duality f L =x 1 x 3 +x 2 x 4 g L =x 1 x 2 +x 3 x 4 f L ≠ g L D

27. Suggested Readings  Moore, E. F., & Shannon, C. E. (1956). Reliable circuits using less reliable relays. Journal of the Franklin Institute, 262(3), 191-208.  Von Neumann, J. (1956). Probabilistic logics and the synthesis of reliable organisms from unreliable components. Automata studies, 34, 43-98.  DeHon, A. (2003). Array-based architecture for FET-based, nanoscale electronics. Nanotechnology, IEEE Transactions on, 2(1), 23-32.  Altun, M., & Riedel, M. D. (2011). Robust Computation through Percolation: Synthesizing Logic with Percolation in Nanoscale Lattices. International Journal of Nanotechnology and Molecular Computation (IJNMC), 3(2), 12-30.