1.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-1 Multiplexers Two alternative forms for a 2:1 Mux Truth Table Functional form Logical form I 1 0 0 0 0 1 1 1 1 I 0 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 S 0 1 Z I 0 I 1 A digital n-to-1 switch is called a multiplexer (or a selector) Z = S' I 0 + S I 1 I 0 I 1 Z S S=0 S=1 2:1 Multiplexor

2.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-2 Multiplexers I 0 S2S2 I 1 I 2 I 3 S1S1 Z 8:1 mux S0S0 I 4 I 5 I 6 I 7 I 0 S1S1 I 1 I 2 I 3 S0S0 Z 4:1 mux 2:1 mux I 0 I 1 S Z

3.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-3 VHDL Muxes LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux4to1 IS PORT( data: INSTD_LOGIC_VECTOR(3 downto 0); sel : IN STD_LOGIC_VECTOR(1 downto 0); z: OUTSTD_LOGIC); END mux4to1; Remember the IEEE library! ARCHITECTURE behavior OF mux4to1 IS BEGIN PROCESS(data,sel) BEGIN CASE sel IS WHEN "00" => z z z z z <= 0; END CASE; END PROCESS; END behavior; Inputs: data[3..0],sel[1..0] Output: Z Set up as a CASE statement WHEN OTHERS – Use this even if there aren’t any others If Data or Sel change, output (Z) can change

4.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-4 Cascading Muxes Large multiplexers can be implemented by cascaded smaller muxes Control signals S 1 and S 0 simultaneously choose one of I 0 -I 3 and I 4 -I 7 Control signal S 2 chooses which of the upper or lower MUX's output to gate to Z Alternative 8:1 Mux Implementation 0 1 S 0 1 S 0 1 S 0 1 S 0 1 S0S0 2 3 S1S1 S2S2 S1S1 S0S0 Z I0I0 I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 I7I7 S0S0 S0S0 S0S0 4:1 mux 4:1 mux 8:1 mux 2:1 mux 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 S2S2 S0S0 S1S1 I0I0 0 1 I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 I7I7 Z

5.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-5 Using Muxes as logic blocks 2 n-1 :1 multiplexer can implement any function of n variables n-1 control variables; remaining variable is a data input to the mux F(C,B,A) = m0 + m2 + m6 + m7 Lookup Table C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 8:1 MUX 1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7S 2 S 1 S 0 CBA F 01 0 1

6.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-6 Optimized LUTs F(C,B,A) = m 3 + m 4 + m 6 + m 7 CB S 1 S 0 4:1 MUX 0 1 2 3 A 0 1 A F We can fit a function of n variables into a 2 n-1 :1 mux by using this trick (note: may require one inverter) C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 0 0 0 1 1 0 1 1 A 0 1 A CB=00; F=0 CB=01; F=A CB=10; F=A’ CB=11; F=1

7.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-7 Using a multiplexor as a switch Consider a computer system with CPU, memory, I/O devices, etc. Each one needs to be able to communicate with the others… Memory CPU Disk Keyboard 4:1 x 32bit Mux 32 Control Pros: Conceptually simple Cons: Lots of wires… Each device needs separate output and input ports 32-bit mux is a large device Example: Read a value from memory into CPU 00

8.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-8 Using a Bus Bus – Bidirectional, Driven by one device at a time Memory CPU Disk Keyboard 32 Control 32 Critical issue: We’re connecting multiple outputs together. Bad Idea! A few (2-3) control lines to each device Pros: Much fewer wires Simpler wiring Expandable One data port per device Cons: More complex electrically Must manage bus Example: Read a value from memory into CPU

9.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-9 Smoke Happens… OK to connect one output to multiple inputs Not OK to connect outputs together! +5V 0 1 Direct connection from power to ground – smoke!

10.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-10 Tri-State Inverter In Out En=1 In Out En=0 In Out En High-Impedance (Hi-Z) state Modify an inverter… Tri-state Inverter Out 5V 0V In Enable EnOut 0Z 1In’

11.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-11 Using tri-state gates Goal: Connect three selectable inputs to a common output Whenever a select signal is asserted, that input is connected to the output Must make sure that there is always exactly one driver turned on! in 0 sel 0 in 1 sel 1 in 2 sel 2 out

12.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-12 Demultiplexers Demultiplexer: One data input, n control inputs, 2 n outputs 1:2 Demultiplexer: O 0 = G S; O 1 = G S G S O0O1O0O1 G S O0O0 O1O1 Control inputs (called selects) - Binary index of output to which the input is connected Data input usually called “enable” (‘G’ or ‘E’)

13.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-13 Larger Demultiplexers/Decoders 1:4 Demultiplexer 1:8 Demultiplexer O 0 = G S 1 S 0 O 1 = G S 1 S 0 O 2 = G S 1 S 0 O 3 = G S 1 S 0 O 0 = G S 2 S 1 S 0 O 1 = G S 2 S 1 S 0 O 2 = G S 2 S 1 S 0 O 3 = G S 2 S 1 S 0 O 4 = G S 2 S 1 S 0 O 5 = G S 2 S 1 S 0 O 6 = G S 2 S 1 S 0 O 7 = G S 2 S 1 S 0 G S 1 S 0 O0O1O2O3O0O1O2O3 G S 2 S 1 S 0 O0O1O2O3O4O5O6O7O0O1O2O3O4O5O6O7 2:4 Decoder 3:8 Decoder If we view the ‘G’ signal as an enable, then a demultiplexer simply decodes the binary select signal into a unary output signal  Decoder Decoder: Enable=0  all outputs are 0 Enable=1  output is unary representation of binary select input

14.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-14 Decoders In VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Decoder2to4 IS PORT( s: INSTD_LOGIC_VECTOR(1 downto 0); en : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR(3 downto 0)); END Decoder2to4; ARCHITECTURE logicfunc OF Decoder2to4 IS BEGIN PROCESS(s,en) BEGIN IF (en=‘1’) THEN CASE (s) IS WHEN “00” => y y y y y <= “0000”; END CASE; ELSE y <= “0000”; END IF; END PROCESS; END logicfunc; Sensitive to changes in s or en Only consider when en = ‘1’ If en = ‘0’, then output “0000” Go through cases for all possible inputs

15.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-15 Encoders Encoders are the opposite of decoders Unary input w[7..0] – exactly one of the eight inputs is ‘1’ Binary output y[2..0] – Corresponds to the index of the input that is ‘1’ For an 8-3 encoder, there should be 256 rows in the truth table Only rows with exactly one ‘1’ are valid  Eight valid rows w0w1w2w3w4w5w6w7w0w1w2w3w4w5w6w7 y0y1y2y0y1y2 8-3 Encoder

16.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-16 Priority Encoders What if more than one input to and encoder is ‘1’?  Invalid input  Output is undefined Priority Encoder: If more than one input is ‘1’, more significant bit has priority Add a ‘z’ output  true when no inputs are ‘1’ w0w1w2w3w4w5w6w7w0w1w2w3w4w5w6w7 y0y1y2y0y1y2 8-3 Priority Encoder z 0 1 0 0 1 0 1 0 1 1 0 0 Higher Priority 6 w7w6w5w4w3w2w1w0y2y1y0z 00000000xxx1 000000010000 0000001x0010 000001xx0100 00001xxx0110 0001xxxx1000 001xxxxx1010 01xxxxxx1100 1xxxxxxx1110

17.  Seattle Pacific University EE 1210 - Logic System DesignMux-Decoder-17 VHDL Priority Encoder LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Priority8 IS PORT( w: INSTD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(2 downto 0); z: OUTSTD_LOGIC); END Priority8; Remember the IEEE library! ARCHITECTURE behavior OF Priority8 IS BEGIN PROCESS(w) BEGIN IF (w(7)=‘1’) THEN y <= “111”; z <= ‘0’; ELSIF (w(6)=‘1’) THEN y <= “110”; z <= ‘0’; ELSIF (w(5)=‘1’) THEN y <= “101”; z <= ‘0’; ELSIF (w(4)=‘1’) THEN y <= “100”; z <= ‘0’; ELSIF (w(3)=‘1’) THEN y <= “011”; z <= ‘0’; ELSIF (w(2)=‘1’) THEN y <= “010”; z <= ‘0’; ELSIF (w(1)=‘1’) THEN y <= “001”; z <= ‘0’; ELSIF (w(0)=‘1’) THEN y <= “000”; z <= ‘0’; ELSE y <= “000”; z <= ‘1’; END IF; END PROCESS; END behavior; Input: w[7..0] Outputs: y[2..0], Z Case statement would require 256 rows… Use cascaded IFs