1. 邏輯設計 多工器 v.s 解多工器 編碼器 v.s 解碼器

2. LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mux_VHDL IS PORT ( I: IN STD_LOGIC_VECTOR(11 downto 0); S: IN INTEGER RANGE 0 to 11; O : OUT STD_LOGIC ); END; ARCHITECTURE a OF mux_VHDL IS BEGIN mux_VHDL: WITH S SELECT o <= I(0) WHEN 0, I(1) WHEN 1, I(2) WHEN 2, I(3) WHEN 3, I(4) WHEN 4, I(5) WHEN 5, I(6) WHEN 6, I(7) WHEN 7, I(8) WHEN 8, I(9) WHEN 9, I(10) WHEN 10, I(11) WHEN 11; END a ; 多工器的 VHDL 程式

3. 解多工器的 VHDL 程式 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY demux_VHDL_2 IS PORT ( I: INSTD_LOGIC; S: INinteger range 0 to 11; O : OUTSTD_LOGIC_VECTOR(0 to 11) ); END ; ARCHITECTURE a OF demux_VHDL_2 IS begin demux12:PROCESS(S,I) BEGIN IF (s=0) THEN o(0)<=I; else o(0)<='0'; END IF; IF (S=1) THEN o(1)<=I; ELSE o(1)<='0'; END IF; IF (S=2) THEN o(2)<=I; ELSE o(2)<='0'; END IF; IF (S=3) THEN o(3)<=I; ELSE o(3)<='0'; END IF; IF (S=4) THEN o(4)<=I; ELSE o(4)<='0'; END IF; IF (S=5) THEN o(5)<=I; ELSE o(5)<='0'; END IF; IF (S=6) THEN o(6)<=I; ELSE o(6)<='0'; END IF; IF (S=7) THEN o(7)<=I; ELSE o(7)<='0'; END IF; IF (S=8) THEN o(8)<=I; ELSE o(8)<='0'; END IF; IF (S=9) THEN o(9)<=I; ELSE o(9)<='0'; END IF; IF (S=10) THEN o(10)<=I; ELSE o(10)<='0'; END IF; IF (S=11) THEN o(11)<=I; ELSE o(11)<='0'; END IF; END PROCESS demux12; END a;

4. 輸入推一, 選擇器不推時 燈亮一個

5. 編碼器的 VHDL 程式 library ieee; use ieee.std_logic_1164.all; entity encode_VHDL is port( I : in std_logic_vector(11 downto 0); Y : out std_logic_vector(3 downto 0)); end encode_VHDL; architecture a of encode_VHDL is begin E124: PROCESS (I) BEGIN IF I="100000000000" THEN Y <= "1011"; ELSIF I="010000000000" THEN Y <= "1010"; ELSIF I="001000000000" THEN Y <= "1001"; ELSIF I="000100000000" THEN Y <= "1000"; ELSIF I="000010000000" THEN Y <= "0111"; ELSIF I="000001000000" THEN Y <= "0110"; ELSIF I="000000100000" THEN Y <= "0101"; ELSIF I="000000010000" THEN Y <= "0100"; ELSIF I="000000001000" THEN Y <= "0011"; ELSIF I="000000000100" THEN Y <= "0010"; ELSIF I="000000000010" THEN Y <= "0001"; ELSIF I="000000000001" THEN Y <= "0000"; ELSE Y<="UUUU"; END IF; END PROCESS ; END a;

6. 解碼器的 VHDL 程式 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode_VHDL IS PORT ( I : ININTEGER RANGE 0 TO 11; Y : OUTSTD_LOGIC_VECTOR(11 downto 0) ); END decode_VHDL; ARCHITECTURE a OF decode_VHDL IS BEGIN decode_VHDL: WITH I SELECT Y <= "000000000001" when 0, "000000000010" when 1, "000000000100" when 2, "000000001000" when 3, "000000010000" when 4, "000000100000" when 5, "000001000000" when 6, "000010000000" when 7, "000100000000" when 8, "001000000000" when 9, "010000000000" when 10, "100000000000" when 11; END a ;

7. 左邊為編碼器, 右邊為解碼器

8. 指撥器推 0001 時, 燈亮一