1. Controllers ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr. Filip Cuckov

2. Overview 1.Algorithmic State Machines 2.Microprogrammed Controllers

3. 1. Algorithmic State Machines (ASM)

4. ASM – Parallel vs. Serial Form =

5. ASM Examples ==

6. Finite State Machine (FSM) to ASM

7. Shift and Add Multiplier Example (Algorithm)

8. Shift and Add Multiplier Example (FSM)

9. Shift and Add Multiplier Example (Counter)

10. Shift and Add Multiplier Example (ASM)

11. Shift and Add Multiplier Example (VHDL)

12. State Machine Factorization using Inter-Process Communication

13. State Machine VHDL Formalism VHDL implementation must include at least 3 processes: 1.State Register (CLK) 2.NS Calc. (PS, Inputs) 3.Outputs Calculation Moore Outputs (PS) Mealy Outputs (PS, Inputs) Fourth Process for Sync. Mealy 4. Output Register (CLK)

14. Moore-Type Machine VHDL Implementation library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MooreSM is generic(N : integer := 3); port( clk, rst : in std_logic; inputs : in std_logic_vector(N downto 0); outputs : out std_logic_vector(N downto 0) ); end entity MooreSM; architecture Behavioral of MooreSM is type state_type is (Start, State1, State2); signal PS, NS : state_type; begin State_Reg : process(clk, rst) is begin if rst = '1' then PS <= Start; elsif clk'event and clk = '1' then PS <= NS; end if; end process State_Reg; NS_Calc : process(PS, inputs) is begin case PS is when Start => NS <= State1; when State1 => if inputs = "0110" then NS <= State2; else NS <= State1; end if; when State2 => NS <= Start; end case; end process NS_Calc; Moore_out : process(PS) is begin case PS is when Start => outputs <= "0000"; when State1 => outputs <= "0110"; when State2 => outputs <= "1001"; end case; end process Moore_out; end architecture Behavioral;

15. Mealy-Type Machine VHDL Implementation library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MealySM is port( clk, rst : in std_logic; A_i, B_i : in std_logic; Y_o, Z_o : out std_logic ); end entity MealySM; architecture Behavioral of MealySM is signal PS, NS : integer range 0 to 2; begin State_Reg : process(rst, clk) is begin if rst = '1' then PS <= 0; elsif rising_edge(clk) then PS <= NS; end if; end process State_Reg; NS_calc : process(PS, A_i, B_i) is begin case PS is when 0 => NS <= 1; when 1 => if (A_i and B_i) = '1' then NS <= 1; else NS <= 2; end if; when 2 => NS <= 0; end case; end process NS_calc; Mealy_out : process(PS, A_i, B_i) is begin Y_o <= '0'; Z_o <= '0'; case PS is when 0 => null; when 1 => if (A_i and B_i) = '1' then Y_o <= '1'; else Z_o <= '1'; end if; when 2 => null; end case; end process Mealy_out; end architecture Behavioral;

16. 2. Microprogrammed Controllers Single Qualifier – Dual Transition Meaning only one Boolean check per state is allowed. Still Single Qualifier – Dual Transition, but NSF assumed to be next in sequence in ROM

17. Microprogrammed Controllers ASM Adjust Mealy to Moore Simplification

18. Microprogrammed Controllers