1. Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Started at: Spring 2012 Duration: Semester

2.  What is SAT  Reminder - description and goals  Memory Technique  GSAT  Flow diagram  Controller  Circuit diagram  Resources usage and times  Runtimes  Conclusions  Notes

3.  Boolean Satisfiability Problem  Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true?  e.g., given the formula f=(x1 ˅ x3 ˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’

4. *Clock frequency is 50M [Hz]

6.  In the first project this was our “what’s next” slide.  Two approaches  Improving compilation times by:  Understanding Altera compilation algorithms to enable faster SAT-specific FPGA ready files.  Smart use of memory on FPGA to implement SAT.  Improving runtimes by designing smart sat solver instead of inefficient LFSR random generator

7.  Two memory entities  SAT is represented by ROM.  Based on the DE2’s M4K built in memory blocks.  We convert the DIMACS CNF SAT instance into a memory description file and put it in the memory.  The ROM address = variable’s number.  content of the address = representation of the clauses which the variable appears in.  Each clause is represented by a shift register that will save the number of variables that satisfy each clause according to the current assignment.

8. c Example CNF format file c p cnf 4 3 1 3 -4 0 4 0 2 -3 0 Example.cnf DEPTH = 4 ; % Variables % WIDTH = 6 ; % Clauses*2 % ADDRESS_RADIX = DEC; DATA_RADIX = BIN; CONTENT BEGIN 0 : 000011; 1 : 110000; 2 : 100011; 3 : 001110; END; Example.mif 0123 0010 For assignment 1101 Clause number 1’s shift register status will be:

10. GSAT(int Maxtries, int Variables) { For (i=1 to Maxtries) { V = a random instantiation of the variables; For (i = 1 to Variables) { p = variable – who’s negation yields largest increase in number of satisfied clauses; V = V with p flipped; } if (F(V) is true) return V; } *Take random variable in case of equality.

11.  Initialize random assignment 01111  Total satisfied clauses = 20 (out of 21)  Flip each variable and see how many added satisfied clauses:  Variable 1 : 0 new satisfied clauses.  Variable 2 : -1 new satisfied clauses.  Variable 3 : -2 new satisfied clauses.  Variable 4 : 0 new satisfied clauses.  Variable 5 : 1 new satisfied clauses.  Maximum = variable 5, flip it.  Assignment = 11111.  Total satisfied clauses = 21 (out of 21) => SUCCESS!

12. New CNF instance Memory Description File FPGAResults Convert In System Memory Content Editor SignalTap Reset

13. Init Reset circuit Random Assignment Clauses Init Var by var run and save to shiftreg Flipping Flip variable value Sum satisfied clauses Advance var Maximum Increase attempts if max <= 0 Flip max var and save to shiftregFinish Output satisfying assignment var == total vars satisfied == total clauses attempts == allowed

15.  LEs: 20,562/33,216 (62%)  M4Ks: 102/105 (97%)  Registers: 8,355/34,593 (24%)  Compilation time: 4:12 minutes.

16. *Clock frequency is 12.5M [Hz] (compared to 50M [Hz])

17.  Runtime was reduced DRASTICALLY.  Due to GSAT implementation.  From data appears to be polynomial increase of 4 th order.  We expect the more the number of variables is the polynomial relationship will decrease, again due to a much harder locality problem.  Random runtimes for same instance due to initial random assignment.  Two degrees of freedom: total attempts, random bit.  can improve runtimes.  Compilation time = NO compilation time.  Use Quartus’s built-in In Memory Content Editor to change the SAT for all variables sizes.

18.  Tried two approaches for clauses representation in memory:  Encoded Clause Representation  For each variable, only clauses which the variable appears in are included in the memory and are represented by binary encode of the clause number.  Less memory usage, more LEs, alters sat, only 14 clauses per variable  special design (decoders, special software support).  Direct Clause Representation  All the clauses are included in the memory each is represented by two bits to indicate if the variables appears in it and what value satisfies it.  More memory usage, less LEs, doesn’t restrict design.  We have developed two Java based applications  SAT converter from cnf to mif format according to our clause representation.  SAT satisfying value asserter.  Currently our design supports 5-sat (5 variables per clause) only, can be increased with minimal effort.

19.  Support maximum of 200 variables and 860 clauses due to the limit of the M4Ks (of the DE2).  408Kb of memory was used.  To measure runtimes we have used benchmark SAT instances, as well as cpp based satisfiable/unsatisfiable SAT generator used in official SAT competitions which was used for runtimes analysis.  We have measured between 4 to 6 instances of SAT with the same variable number and took the average.  The standard deviation of the runtimes was of the same order of the average, meaning that the results vary a lot between instances due to the local minimum problem.

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21.  Thank you!  Questions?