1. http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS inverters http://www.eet.bme.hu/~poppe/miel/en/13-MOSFET2.ppt

2. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 2 Overview of MSOFET types

3. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 3 Characteristics of enhancement mode MOSFETs Now we calculate with this! inversion layer saturation triode region

4. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 4 Simple model of MSOFETs ► The simplest (logic) model:  mo conduction (off) / conduction (on) Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on "open" "short" enhancement mode device

5. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 5 Let's construct an inverter! ► Resistor at supply voltage (V DD ) ► Other end connected to ground (GND) through a swithc ► Switch controlled by a logic signal:  1 (V DD level) – "short"  0 (GND level) – "open" ► The output is the common node of the switch and the resistor V DD GND IN OUT load resistor

6. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 6 Let's construct an inverter! ► IN = 1  switch "on"  aoutput connected to GND  OUT = 0 V DD GND IN OUT 1 0 V DD GND IN OUT ► IN = 0  switch "off"  output floating at V DD  OUT = 1 0 1

7. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 7 Two switches in series: NAND gate V DD GND OUT A B ► If A and B equal to 1, then OUT=0 ► This is the NOT (A AND B) function, i.e. NAND serial conduction path If there are parallel conductions paths then we get the NOR function In practice with max. 3..4 inputs.

8. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 8 The scheme of the NOR gate: V DD GND OUT AB PARALLEL conduction path GND ► If A or B equals to 1, then OUT=0 ► This is the NOT (A OR B) function, i.e. NOR Complex conduction paths == option for complex logic gates

9. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 9 Complex logic gates ► Serial paths connected in parallel V DD GND OUT AB C DEF There are 4 paths

10. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 10 Inverter realizations V DD GND IN OUT Switch = n channle MOSFET: normally OFF device V DD GND IN OUT Load resistor: another transistor, e.g. in triode region V DD GND IN OUT V GG Needs another supply – not OK load drive

11. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 11 nMOS technique – very simple ► Simple process, outdated, many disadvantages  static consumption if OUT=0  if OUT = 0, it will not be a pure GND level  asymmetrical transfer characteristic (see later) BE ► In both cases the load resistor is replaced by a MOSFET but this transistor was not provided with an active control  This is the passive load inverter Kiürítéses tr.: implantációval eltolt V T V DD GND KI I d ~ W/L

12. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 12 Complex gates (in nMOS) ► Serial conduction paths in parallel, e.g.: There are 4 paths OUT

13. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 13 The CMOS technique ► The name comes from: Complementary MOS ► Idea: the load also should be provided with active control  if the nMOS driver (switching) trasistor conducts the load transistor legyen must be an "open" circuit  if the nMOS driver (switching) trasistor is an "open circuit", the load must be conducting ► This needs such a normally OFF device which needs "opposite" control signals than the nMOS transistors  Such device is a pMOS transistor

14. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 14 The CMOS inverter V DD GND OUT IN nMOS pMOS ► An n and a p type enhancement mode device ► Active load inverter: the two transitors have the same common control In steady state only one device is "on", the other is "off".

15. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 15 Characteristics of inverters, rudiments ► Transfer characteristic:  output voltage vs. input voltgae The output signal is the inverted version of the logic value of the input signal transfer characteristic of an ideal and a realistic inverter

16. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 16 Xfer char. of a CMOS inverter V DD GND OUT IN nMOS pMOS U IN =U GSn U OUT =U DSn

17. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 17 Characteristics of inverters, rudiments ► Noise immunity:  Same U out corresponds to a wide U in range  There are 3 regions in the charactersitic  On the L and H sides the characteristc is flat, i.e. any voltage change in the input has negligible effect on the output. L and H regions L H transfer characteristic of an ideal and a realistic inverter

18. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 18 Characteristics of inverters, rudiments ► Signal regeneration  depends on the slope of the middle region U 1 is a "bad" logic 0 signal. Output U 2 of the first inverter is already close to an acceptable logic 1 level. output voltage U 3 at the second inverter is already a "good" logic 0 level. U2U2 U1U1 U2U2 U3U3 U in U out "1" "0" transfer characteristic of an ideal and a realistic inverter

19. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 19 Characteristics of inverters, rudiments ► Signal regeneration U3U3 U2U2 U1U1 0.0n10.0n20.0n30.0n40.0n time [sec] -0.0 1.0 2.0 3.0 4.0 5.0 6.0 U [V] In case of U 3 both the voltage level and the signal form are visibly regenerated! U L =0V, U H =5V (SPICE simulation)

20. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 20 Characteristics of inverters, rudiments ► Inverter logic threshold voltage The level, under which the signals will be converted into logical 0 and above which the signals will be converted by the inverter chain into logical 1 Intersection of the U in =U out line and the x-fer characteristic U in U out V dd UkUk

21. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 21 Characteristics of inverters, rudiments ► Logic level ranges The voltage range of the logic 0 and 1 values within which the circuit works safely in the respective logic level U in U out V dd UkUk U Hm UZUZ Important voltage values U LM, max. of logic 0 U Hm, min. op logic 1 U LM Example: 74HC00, V dd =3V, U LM =0.9V U Hm =2.1V

22. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 22 Characteristics of inverters, rudiments ► Propagation delay t pd is difficult to define, and may be different for switching on and off (e.g. nMOS inverters)

23. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 23 Characteristics of inverters, rudiments ► Inverter pair delay A long chain of uniform inverters is assumed. After a certain number of inverters the signal form will be determined by the inverter properties only. After propagating throug 2 inverters the signal will be the same, the delay will be t pdp – the inverter pair delay t pdp t UUnUn U n+2 111 nn+2

24. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 24 Characteristics of inverters, rudiments ► Measuring the inverter pair delay THE RING OSCILLATOR Odd number of inverters connected in a chain, no stable state  oscillate 11111 T=n  t pdp

25. Budapest University of Technology and Economics Department of Electron Devices 24-11-2008 Microelectronics BSc course, MOS inverters © András Poppe, BME-EET 2008 25 Characteristics of inverters, rudiments ► Power-delay product (P  )  low power and small delay refer to good quality, the product may be a figure of merit for the quality of a circuit family.  the physical meaning: the minimal energy, needed to work on 1 bit of information.