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In AMIS CMOS 07 by Roman Prokop
Current mirror design In AMIS CMOS 07 by Roman Prokop
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Simple current mirror Saturace
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AMIS CMOS 07 param VT0 & KP = f (T, process) graphs
NMOS Process VT0 [V] Kp [A/V2] Temp [°C] Typ 0.75 27 Fast 0.7 -50 0.45 150 Slow 1.00
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W/L calculation for typ parameters
Choose ∆VGS= 250 mV & ID= 20 μA
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Ideal Vds1=Vds2 solution - Decrease the Vds influence large L - cascoda
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min. ∆VGS max. ∆VGS Then input current can vary between (even for fix (dummy) resistor R) 150°C hipo(min)IIN ↑ °C hipo(max)IIN ↓
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How to get fixed voltage for current mirror biasing ?
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How to get fixed voltage for current mirror biasing ?
better – doesn’t depend on Ucc
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Matching hand calculation
Premise - 2 transistors in common centroid (crossquad) - ideal surrounding Instructions in: “Electrical parameters CMOS07” manual (ds13291.pdf) A1 A2 B1 B2 Exemplary calculation – choose W/L=7 W/L= 35u/5u quite small MOS
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Matching Error in VT0 Error in β Statistical errors –
- count under square root For good matching (small current difference) - larger MOS high WL - higher (VGS – VT0)
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Matching Table is valid for NMOS, PMOS parameters in electrical parameters Carefully: units mV, μm, %
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Matching
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Matching Cadence matching tool output file
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Biasing currents Usually use buffered band-gap reference voltage
1 - External resistor - accurate resistance value, almost temperature independent 2 – Hipo internal resistor - hipo resistance Ω (1600 Ω Ω) - temperature dependence - viz. parameterFile 3 – other CMOS resistor types - not used because of small sheet resistance One chip can combine both types of bias currents
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Biasing currents Hipo internal resistor bias current advantages
- temperature dependent current can help with stability of some circuits - quite accurate voltage level shifter Current mirror and resistor MATCHING !!!!
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Cascoded mirror output resistance
express It negligible
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Good luck !!!
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