1. Measurement and data extraction. How to measure the splice and diode interconnections. Accuracy and issues of these measurements. Data extraction issues. Data analysis tools. Z.Charifoulline, TE/MPE-CP 10/7/20111CSCM Workshop

2. t plateau dI/dt I plateau I t FPA if V>V thr dV/dt to open the diodes Fast ramp down if V>V thr t1t2 500 A 4-6 kA 60 s PC in voltage modePC in current mode 500 A/s H. Thiesen – 16 August 2011 – TE-TM Trip by nQPS mBS CSCM current cycles 1 kA How to measure the splice and diode interconnections. “safe” measurements “unsafe” measurements 10/7/20112CSCM Workshop

3. How to measure the splice and diode interconnections. 0.5 – 1kA tests (“safe”): It is safe since any errors in protection thresholds will cause a trip but not yet a burning of any splices or diodes - 60s@1kA ramps to verify new QPS hardware and software - RRR measurements (board A) - R diode measurements at low current (board B – board A) - define, load and verify voltage thresholds of mBS boards 4 – 6kA tests (“unsafe”): It is not safe since a single error in protection thresholds may cost as a burning of defective splice or diode! - 10s@4kA->60s@4kA->10s@5kA->60s@5kA->10s@6kA->60s@6kA (see A.W. talk) - redefine voltage thresholds after every ramp -> reload and verify if needed! - R diode measurements and case analysis for high values before next ramp - correctly detect runaway event if so for detailed off-line analysis later on On this step the tests still can be performed by use of conventional splice protection boards (nQPS BS ) and can be analyzed by existed software (SM), but we need to check new hardware and software. To be able to detect correctly the thermal runaways (or CSCM evnts) we need much faster DAQ. And we need parallel Board A&B measurements to distinguish runaways from high diode lead resistances. So this is why the nQPS mBS board was born! (Jiens child) 10/7/20113CSCM Workshop

4. nQPS BS Board A: EE012 EE013 (Bus bar) nQPS BS Board B: EE014 EE015 (Bus bar + 2 DLs) How to measure the splice and diode interconnections. “nQPS BS” boards will be replaced by “nQPS mBS” boards. But it will be no any additional patches => so voltage taps will be still the same. (see A.W, J.S. talks) 10/7/20114CSCM Workshop

5. Current lead protection (nominal) Board ABoard BMeaning LD1:U_RES EE11 - EE21EE12 - EE22Copper part of C.L. LD1:U_HTSEE21 - EE31EE22 - EE32HTS part of C.L. U_BB_1EE41 - EExxEE42 - EExx From bottom of HTS Copper HTS TT893 (TT811) EE11,EE12 EE21,EE22 EE31, 32 41, 42 HeLiquidlevel PT100 PT100 U_RES U_HTS 1st Magnet: EE012, EE013 (Board A) EE014, EE015 (Board B) 1 st Bus Bar segment We are not going to measure the current leads? The first bus bar segments will be protected and measured exactly the same way as others. (as it is now in the tunnel at cold) Only the difference, that they had never been measured at warm (biddle testing, RRR?) and there is no diode from one side. nQPS 1 st crate: BS or mBS How to measure the current lead interconnections? 10/7/20115CSCM Workshop

6. QP3-simulation: RB Bus Bar, RRR BUS =200, RRR SC =120 Temperature = 20K Length = 30 and 40m Single Side Defect = 2, 10, 20, 30, 40, 50mm Current = 1kA and 6kA Bus Bar Segment Resistance (plus diode leads Board B) Bus Bar Splice Defect How to measure the splice and diode interconnections. 1 kA 6 kA 10/7/20116CSCM Workshop ∆t

7. How to measure the splice and diode interconnections. 1 kA ~60-100s, 5Hz => 300-500 points - U0 1kA values will be calculated and stored for boards A and B - to be used to define 4kA thresholds: U thr = 4*U0 1kA + U safe - (U B – U A ) will be the diode leads voltages (analysis will be added) - bus bar resistances will be calculated (=>RRR, +length or 300K tests) U0 1kA Simulation: RB, Sector12 Real Bus Bar lengths T=20±2K, RRR=200±50 ±50uV noise mBS: 5Hz@305nV Simulation: RB, Sector12 Real Bus Bar lengths T=20±2K, RRR=200±50 ±50uV noise mBS: 5Hz@305nV It would be the nice bus bar length pattern if RRR and T He are constant! Dipole: 15m 55m, but mainly ~30m and ~40m Quads: 100m 250m, but in some cases ~450m! 10/7/20117CSCM Workshop

8. There are important voltage drops to worry about... 10/7/2011CSCM Workshop magnet [BA23.L1 BB22.L1] A23L1 magnet B22L1 splicebridge 11kΩ Cable 2Cable 1 2.2Ω bridge 22kΩ Cable 4Cable 3 5.1Ω 248uV 367mV352mV 14.7A 24mΩ 25mΩ 16uA33uA 82uV 73uV 17uΩ 403uV Correction can be 70% of signal! Length cable 2= 29m Length cable 3= 66m Timber Calculated M.K. TE/MPE, 13-01-2011 1kA 5-40uΩ ~1V 30 … 100m 10 … 40mV ~50uA 250uV ~3-5% So CSCM will be at least one more RRR-measurements within 5% but without complicated corrections and for whole sector. How to measure the splice and diode interconnections. 8

9. 6 kA Simulation: RB, Sector12 Real Bus Bar lengths T=20±2K, RRR=200±50 ±50uV noise mBS: 5Hz@305nV ~30mm defect! - U0 6kA values and thresholds calculated from previous 10s@6kA ramp! - (U B – U A ) will be the diode leads voltages (analysis will be added) Board A 10/7/20119CSCM Workshop ∆t

10. How to measure the splice and diode interconnections. 6 kA Simulation: RB, Sector12 Real Bus Bar lengths T=20±2K, RRR=200±50 ±50uV noise mBS: 5Hz@305nV ~30mm defect! 20µΩ white noise added! (diode leads simulation) Board B - U0 6kA values and thresholds calculated from previous 10s@6kA ramp! - (U B – U A ) will be the diode leads voltages (analysis will be added) It is extremely important to collect and analyze the test data from every ramp > 4kA for both Boards A & B and to define and load correct thresholds for every channel! Thresholds calculation might be not so trivial, especially for dU/dt of board B. 10/7/201110CSCM Workshop

11. 10/7/2011CSCM Workshop11 Data extraction issues and analysis tools. -threshold calculations, U and dU/dt? - saving to proper files for loading - check after loading for data consistency Calculated thresholds

12. 2048 total 30 bus bars > 1.2nΩ 10σ for MB 3σ for MQ MB 301 ± 85pΩ MQ 306 ± 313pΩ nQPS BS (A&B) U_MAG: LSB=1.9µV, Range=±15.9V PtP≈500µV(noise) U_RES: LSB=1.5nV, Range=±12.8mV PtP≈50µV-100µV (noise) 5Hz, 50points moving average (10s) 2048 channels (x2) Logging DB U_RES(t), U_MAG(t) I_MEAS(t) Magnet Bus Bar 1 23 4 Data extraction issues and analysis tools. nQPS BS: Cold Splice Protection and Measurement 10/7/201112CSCM Workshop

13. nQPS mBS (A&B) U_MAG: LSB=1.9µV, Range=±15.9V PtP≈500µV(noise) U_RES: LSB=305nV, Range=±2.5V PtP≈50µV-100µV (noise) 16.5Hz, no filtering 2048 channels (x2) Logging DB U_RES(t) I_MEAS(t) Magnet Bus Bar 1 23 4 nQPS mBS: CSCM Main changes: - 16.5Hz DAQ, no filtering; - 5Hz data available in logging DB; - 16.5Hz@3000 internal buffers (for boards A&B!) ; (see J.S. talk) Data extraction issues and analysis tools. A&B Buffers extractions need to be added to the existing data flow. 10/7/201113CSCM Workshop 5Hz from TIMBER or Front End T=20K R BB_dipole = 0.36µΩ/m => 10-20mV@1kA R BB_quad = 0.57µΩ/m => 50-250mV@1kA R diode lead = 5-20µΩ => 30-120mV@6kA

14. Data extraction issues and analysis tools. By courtesy of A.Gorzawski Test 3minBuffers extraction2x15min 3000@16.6Hz, ~180s By Test Operator Special Macro or LabView It will give absolute time reference for all curves within ±200ms and guarantee correct analysis of runaways By Test Operator Special Macro or LabView Application will toggle ST_BOARD_A to avoid board mixture Finally Test Data stored in Logging DB and ready for analysis. But the timescales need to be correctly reconstructed (5Hz -> 16.5Hz) 10/7/201114CSCM Workshop

15. Data extraction issues and analysis tools. By courtesy of A.Gorzawski 10/7/201115CSCM Workshop Data stored in Logging DB and ready for analysis. But the timescales still need to be correctly reconstructed (5Hz -> 16.5Hz) DS buffers reading application - adapted already for mBS buffers. Data can be saved and analyzed in EXCEL. Arkadiusz QPS DB (develop.) -BS signals -DS signals -Bus Bar Lengths -Splice cold resistances - and many more …

16. 10/7/201116CSCM Workshop Data extraction issues and analysis tools. Summary: - mBS DAQ is sensitive and fast enough to make measurements at mV ranges; - bus bar RRR can be re-measured within 3-5% (will depend on T He stabilization); - mSB buffers triggering and extraction procedures established and checked; - all data will be saved to logging DB with absolute time stamps (<1s) and A/B signatures, which allow correct off-line expert’s analysis; -Special Java Application developing to read the data from logging DB, to reconstruct the timescales, to save data to csv-files or to QPS DB for online analysis of the whole considered sector. -Splice Monitor application (or new) will be upgraded for new requirements: - board A/B analysis, thresholds estimations and preparing for loading; - diode leads resistance evaluation from two boards data; - and needs to be very reliable and be checked before going to high currents;

17. 10/7/2011CSCM Workshop17 Thanks!

18. RB, 30m, 6kA How to measure the splice and diode interconnections. 40mm, 15K, 20K, 25K 15K, 20K, 25K 30mm He-Bath temperature variation effect 10/7/201118CSCM Workshop

19. Diode lead ‘resistances’ for 6 kA quenches Conclusion: Large spread among the 12 leads. ‘Steps’ occurring in first 15 s. 5  : maximum measured at reception in SM18 13  : specification during reception in SM18 10/7/201119CSCM Workshop

20. Diode lead ‘resistances’ for B15R5 Anode Conclusion: Inductive signal is small. Results indicate the presence of one or more irregular contacts. The three 6 kA curves differ a factor 2. 10/7/201120CSCM Workshop

21. Resistance of the heat sink at 10 K with RRR=100 0.001  Resistance of the lower diode bus at 10 K with RRR=100 (upper heat sink) 0.17  Resistance of the lower diode bus at 10 K with RRR=100 (lower heat sink) 0.28  Resistance of the upper diode bus at 10 K with RRR=100 0.23  Power in a diode at 2 kAAbout 2.4 kW Power in a diode at 6 kAAbout 6.6 kW Energy needed to warm up the helium inside the diode from 1.9 to 2.17 K1.4 kJ Energy needed to warm up the helium inside the diode from 2.17 to 4.3 K5.1 kJ Energy needed to evaporate the helium inside the diode14 kJ Energy needed to warm up both heat sinks from 1.9 to 4.3 K4 J (see next plot) Temperature rise of the diode lead (RRR=100, adiab.) for 6 kA, t=50 s decay1.9 K to 31.3 K Resistance rise of the diode lead (RRR=100, adiab.) for 6 kA, t=50 s decay 0.59 to 0.86  Resistance of the lower diode lead at 110 K 4.6 to 7.7  Temperature rise of the heat sink (adiab.) for 6 kA, t=50 s decay1.9 K to 110 K Some numbers 10/7/201121CSCM Workshop