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Chapter 5 Computer Systems Organization. Levels of Abstraction – Figure 5.1e The Concept of Abstraction.

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Presentation on theme: "Chapter 5 Computer Systems Organization. Levels of Abstraction – Figure 5.1e The Concept of Abstraction."— Presentation transcript:

1 Chapter 5 Computer Systems Organization

2 Levels of Abstraction – Figure 5.1e The Concept of Abstraction

3 Levels of Abstraction – Figure 5.1b The Concept of Abstraction (Continued)

4 Levels of Abstraction – Figure 5.1c The Concept of Abstraction (Continued)

5 Levels of Abstraction – Figure 5.1d The Concept of abstraction (Continued)

6 Levels of Abstraction – The Hierarchy of Abstraction

7 Figure 5.2 The Von Neumann Architecture

8 Memory and Cache – Figure 5.3 Structure of Random Access Memory

9 Memory and Cache – Figure 5.5 Organization of Memory and Decoding Logic

10 The Von Neumann Architecture - Figure 5.6 - Two- Dimensional Memory Organization

11 The Von Neumann Architecture – Figure 5.7 Overall RAM Organization

12 Memory and Cache – The Organization of the “two- level memory hierarchy” is the above

13 Input/Output and Mass Storage – A Disk Stores Information in Units called “sectors” Each of Which Contains an Address and a Data Block

14 Input/Output and Mass Storage – A Fixed Number of Sectors on the Surface of a Disk are Called a Track

15 Input/Output and Mass Storage – Figure 5.8 Overall Organization of a Typical Disk

16 Practice Problem – Figure 5.9 Organization of the 1/0 Controller

17 The Arithmetic/Logic Unit – Figure 5.10 Three-Register ALU Organization

18 The Arithmetic/Logic Unit – Figure 5.11 Multiregister ALU Organization

19 The Arithmetic/Logic Unit – Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result

20 The Arithmetic/Logic Unit Figure 5.13 Overall ALU Organization

21 The Control Unit – Figure 5.14 Typical Machine Language Format

22 The Control Unit – The Address Fields

23 Machine Language Instructions – Figure 5.15 Examples of Simple Machine Language Instruction Sequence

24 Control Unit Registers and Circuits – Figure 5.16 Organization of the Control Unit Registers and Circuits

25 Control Unit Registers and Circuits – Figure 5.17 The Instruction Decoder

26 Putting All The Pieces Together – Figure 5.18 The Organization of a Von Neumann Computer

27 Figure 5.25 Graph of Computer Speeds 1945 to the Present

28 The Future: Non-Von Neumann Architectures – Figure 5.26 A SIMD Parallel Processing System

29 The Future: Non-Von Neumann Architectures – Figure 5.27 Model of MIMD Parallel Processing


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