1. Eduardo L. Rhod, Álisson Michels, Carlos A. L. Lisbôa, Luigi Carro ETS 2006 Fault Tolerance Against Multiple SEUs using Memory-Based Circuits to Improve the AVF Technology trends for semiconductors forecast a higher incidence of soft errors caused by radiation in digital circuits implemented using sub 65nm technologies. New design approaches are necessary to generate circuits that are able to withstand multiple simultaneous upsets. Traditional fault tolerance approaches like TMR do not support multiple SEUs. Results show that even N-MR techniques do not work as expected. Several error detection and correction codes have been proposed, but most of them do not correct multiple bit flips, or when they do, the overhead in area and / or performance is not acceptable. Porto Alegre - RS BRAZIL e-mail eduardo.rhod@ufrgs.br alisson.michels@ufrgs.br calisboa@inf.ufrgs.br carro@inf.ufrgs.br Universidade Federal do Rio Grande do Sul - UFRGS Programa de Pós-Graduação em Engenharia Elétrica Programa de Pós-Graduação em Computação http://www.ufrgs.br/ppgee, http://www.inf.ufrgs.br/pos/ppgc Conclusions  Experiments have shown that the proposed technique reduces the AVF up to 30 times.  The bad results for the 5-MR solution are due to the increased unprotected circuit area for voters, when compared to TMR. Introduction Results 4x4-bit Multiplier AVF and Timing for Single and Double Faults Future Work  Test the proposed approach with different case studies  Use this technique to implement a memory-based processor Memories using emerging technologies, like magnetic RAMs, are not affected by high energy particle strikes. This work proposes to replace parts of combinational circuits with intrinsically protected memories, thus reducing the overall architectural vulnerability factor (AVF), and, consequently, the soft error rate (SER). Replacing combinational circuits with memory (the memory works as a truth table !) Example: 4x4-bit multiplier Combinational only Memory only Total area = 304 transistors Memory Input A 4 Input B 4 Result 8 8 inputs and 8 outputs Total area = 2,048 transistors (considering 1 transistor per bit) Expensive !!! Case Study: 4x4-bit Multiplier B0 B1 B2 B3 Memory Register Result Shift- Register P6 P5 P4 P3 P2 P1 P0 P7 0 A0 A1 A2 A3 0 A0 A1 A2 A3 0 A0 A1 A2 A3 0 A0 A1 A2 A3 Counter for mux selection signals 3 1) Column Multiplier Circuit sensitive to faults A0 A1 A2 A3 Memory Result Shift- Register P3 P2 P1 P0 P7 P6 P5 P4 B0 B1 B2 B3 Counter for mux selection signals 4 bit Register 2) Line Multiplier Circuit sensitive to faults Case Study: 4-tap, 8-bit FIR filter ROM MEMORY (COEFFICIENTS) IN0 IN1 IN3 1 1 1 + IN2 1 10 REGISTER 10 11 y[6]y[7]y[5]y[4]y[3]y[2]y[1]y[0]y[17]..... y[8] 10 Circuit sensitive to faults Circuit #of gates that fail AVF % (1 fault) AVF % (2 faults) Prop. AVF % (1 fault) Prop. AVF % (2 faults) Critical Path Timing (ns) 5-MR 4928.8020.508.8020.5018.5 TMR 2685.4916.262.998.8618.2 Combin. 7649.1163.607.599.8217.5 Column 3315.9228.051.071.8815.0 Line 936.2254.070.660.9916.5 Circuit #of gates that fail Prop. AVF % (1 fault) Prop. AVF % (2 faults) Critical Path Timing (ns) Combinational 163148.2167.3569.0 Memory Based 501.392.117.1 FIR Filter AVF and Timing for Single and Double Faults